P0130AA

4/5

Fig. 4: Relative variation of gate trigger current,

holding current and latching current versus

junction temperature (typical values).

Fig. 5:Relative variation of holding current versus

gate-cathode resistance (typical values).

Fig. 6: Relative variation of dV/dt immunity

versus gate-cathode resistance (typical values).

Fig. 7: Relative variation of dV/dt immunity

versus gate-cathode capacitance (typical values).

Fig. 8:

Surge peak on-state current versus

number of cycles.

Fig. 9:

Non-repetitive surge

peak on-state

current

for

a

sinusoidal

pulse

with

width

tp < 10 ms, and corresponding value of I²t.

IGT, IH, IL[Tj] / IGT, IH, IL[T] = 25°C

6

5

4

3

2

1

0

0

-20

-40

20

40

60

80

100

120

140

Tj(°C)

IH[Rgk]/IH[Rgk=1k ]

Ω

Rgk(k

Ω)

0.4

0.6

0.8

1.0

0.2

1.6

1.8

2.0

1.2

1.4

dV/dt[Rgk] / dV/dt[Rgk=1k ]

Ω

Rgk(k

Ω)

0

0.1

1.0

10.0

dV/dt[Cgk] / dV/dt[Rgk=1k ]

Ω

2

1

03

4

5

6

7

0

2

4

6

8

10

Cgk(nF)

1

10

100

1000

0

1

2

3

4

5

6

7

8

ITSM(A)

Non repetitive

Tj initial=25°C

Tamb=25°C

Repetitive

Numberofcycles

Onecycle

tp=10ms

ITSM(A), I t(A s)

22

100.0

10.0

1.0

0.1

0.01

0.10

1.00

10.00

tp(ms)