CAT1161WI-28-T3 datasheet(9/14 Pages) CATALYST

部品番号	CAT1161WI-28-T3

部品情報	Supervisory Circuits with I2C Serial CMOS EEPROM, Precision Reset Controller and Watchdog Timer (16K)

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CAT1161, CAT1162

9

Doc. No. MD-3002 Rev. G

Characteristics subject to change without notice

Acknowledge Polling

Disabling of the inputs can be used to take

advantage of the typical write cycle time. Once the

stop condition is issued to indicate the end of the

host’s write opration, the CAT1161/2 initiates the

internal write cycle. ACK polling can be initiated

immediately. This involves issuing the start condition

followed by the slave address for a write operation. If

the CAT1161/2 is still busy with the write operation,

no ACK will be returned. If a write operation has

completed, an ACK will be returned and the host can

then proceed with the next read or write operation.

WRITE PROTECTION

The Write Protection feature allows the user to

protect against inadvertent memory array program-

ming. If the WP pin is tied to VCC, the entire memory

array is protected and becomes read only. The

CAT1161/2 will accept both slave and byte

addresses, but the memory location accessed is

protected from programming by the device’s failure

to send an acknowledge after the first byte of data is

received.

READ OPERATIONS

The READ operation for the CAT1161/2 is initiated in the

same manner as the write operation with one exception,

that R/W

¯¯ bit is set to one. Three different READ ope–

rations are possible: Immediate/Current Address READ,

Selective/Random READ and Sequential READ.

Immediate/Current Address Read

The CAT1161/2 address counter contains the address

of the last byte accessed, incremented by one. In other

words, if the last READ or WRITE access was to

address N, the READ immediately following would

access data from address N+1. For all devices,

N=E=2047. The counter will wrap around to Zero and

continue to clock out valid data for the 16K devices.

After the CAT1161/2 receives its slave address

information (with the R/W

¯¯ bit set to one), it issues an

acknowledge, then transmits the 8-bit byte requested.

The master device does not send an acknowledge, but

will generate a STOP condition.

Figure 9. Immediate Address Read Timing

SCL

SDA

8TH BI T

STOP

NO ACK

DATA OUT

89

SLAVE

ADDRESS

S

A

C

K

DATA

N

O

A

C

K

S

T

O

P

BUS ACTIVIT Y:

MASTER

SDA LINE

S

T

A

R

T

同様の部品番号 - CAT1161WI-28-T3

メーカー	部品番号	データシート	部品情報
Catalyst Semiconductor	CAT1161WI-28-GT2	163Kb / 14P	Supervisory Circuits with I2C Serial CMOS EEPROM, Precision Reset Controller and Watchdog Timer
Catalyst Semiconductor	CAT1161WI-28-GT3	163Kb / 14P	Supervisory Circuits with I2C Serial CMOS EEPROM, Precision Reset Controller and Watchdog Timer
ON Semiconductor	CAT1161WI-28-GT3	193Kb / 14P	Supervisory Circuits with I2C Serial CMOS EEPROM, Precision Reset Controller and Watchdog Timer (16K) Doc. No. MD-3002 Rev. I
	CAT1161WI-28-GT3	163Kb / 13P	Supervisory Circuits with I2C Serial CMOS EEPROM, Precision Reset Controller and Watchdog Timer (16K) July, 2012 - Rev. 12
	CAT1161WI-28-GT3	163Kb / 13P	Supervisory Circuits with I2C Serial CMOS EEPROM, Precision Reset Controller and Watchdog Timer (16K) July, 2012 ??Rev. 12

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同様の説明 - CAT1161WI-28-T3

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