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CS4953XX データシート(PDF) 3 Page - Cirrus Logic |
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CS4953XX データシート(HTML) 3 Page - Cirrus Logic |
3 / 38 page CS4953xx Data Sheet 32-bit Audio Decoder DSP Family DS705PP2 ®Copyright 2008 Cirrus Logic, Inc. 3 8.2 144-Pin LQFP Pinout Diagram ............................................................................................................... 33 9. Package Mechanical Drawings ..............................................................................................34 9.1 128-pin LQFP Package Drawing ............................................................................................................ 34 9.2 144-Pin LQFP Package .......................................................................................................................... 35 10. Revision History ....................................................................................................................36 List of Figures Figure 1. RESET Timing ........................................................................................................................................12 Figure 2. XTI Timing ..............................................................................................................................................12 Figure 3. Serial Control Port - SPI Slave Mode Timing ..........................................................................................14 Figure 4. Serial Control Port - SPI Master Mode Timing ........................................................................................15 Figure 5. Serial Control Port - I2C Slave Mode Timing ..........................................................................................16 Figure 6. Serial Control Port - I2C Master Mode Timing ........................................................................................17 Figure 7. Parallel Control Port - Intel® Mode Read Cycle ......................................................................................19 Figure 8. Parallel Control Port - Intel Mode Write Cycle ........................................................................................19 Figure 9. Parallel Control Port - Motorola® Mode Read Cycle Timing ...................................................................21 Figure 10. Parallel Control Port - Motorola Mode Write Cycle Timing ...................................................................21 Figure 11. UART Timing ........................................................................................................................................22 Figure 12. Digital Audio Input (DAI) Port Timing Diagram .....................................................................................23 Figure 13. Direct Stream Digital - Serial Audio Input Timing ..................................................................................24 Figure 14. Digital Audio Port Timing, MCLK Master Mode ....................................................................................25 Figure 15. External Memory Interface - Flash Write Cycle Timing .........................................................................27 Figure 16. External Memory Interface - Flash Read Cycle Timing ........................................................................27 Figure 17. External Memory Interface - SDRAM Burst Read Cycle .......................................................................29 Figure 18. External Memory Interface - SDRAM Burst Write Cycle .......................................................................29 Figure 19. External Memory Interface - SDRAM Auto Refresh Cycle ....................................................................30 Figure 20. External Memory Interface - SDRAM Load Mode Register Cycle ........................................................30 Figure 21. 128-Pin LQFP Pin-Out Drawing ............................................................................................................32 Figure 22. 144-Pin LQFP Pin-Out Drawing ............................................................................................................33 Figure 23. 128-Pin LQFP Package Drawing .........................................................................................................34 Figure 24. 144-Pin LQFP Package Drawing .........................................................................................................35 List of Tables Table 1. CS4953xx Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 2. Device and Firmware Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. CS495303 DSP Memory Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 4. CS495313 DSP Memory Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 5. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 6. Environmental, Manufacturing, & Handling Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 7. 128-Pin LQFP Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 8. 144-Pin LQFP Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 |
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同様の説明 - CS4953XX |
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