9

STK14C88-3

Feb, 2008

Document Control #ML0015 Rev 2.0

SOFTWARE STORE/RECALL MODE SELECTION

e

Note r:

The six consecutive addresses must be in the order listed. W must be high during all six consecutive E controlled cycles to enable a nonvola-

tile cycle.

Note s:

While there are 15 addresses on the STK14C88-3, only the lower 14 are used to control software modes.

Note t:

Note u:

The software sequence is clocked on the falling edge of E controlled READs without involving G (double clocking will abort the sequence).

See application note:MA0002 http://www.simtek.com/attachments/AppNote02.pdf.

Note v:

The six consecutive addresses must be in the order listed in the Software STORE/RECALL Mode Selection Table: (0E38, 31C7, 03E0, 3C1F,

303F, 0FC0) for a STORE cycle or (0E38, 31C7, 03E0, 3C1F, 303F, 0C63) for a RECALL cycle. W must be high during all six consecutive

cycles.

E

W

MODE

I/O

POWER

NOTES

L

H

0E38

31C7

03E0

3C1F

303F

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Output Data

Output Data

Output Data

Output Data

Output Data

Active

n, r, s, t

0FC0

Nonvolatile

STORE

Output High Z

L

H

0E38

31C7

03E0

3C1F

303F

0C63

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Nonvolatile

RECALL

Output Data

Output Data

Output Data

Output Data

Output Data

Output High Z

Active

n, r, s, t

NO.

SYMBOLS

PARAMETER

STK14C88-3-

35

STK14C88-3-

45

UNITS NOTES

Standard

Alternate

MIN

MAX

MIN

MAX

33

STORE

/RECALL Initiation Cycle Time

35

45

ns

n

34

Address Set-up Time

0

0

ns

u, v

35

Clock Pulse Width

25

30

ns

u,v

36

Address Hold Time

20

20

ns

u, v

37

RECALL

Duration

20

20

μs

DATA VALID

HIGH IMPEDANCE

ADDRESS #6

ADDRESS #1

DATA VALID

33

DATA VALID

DQ (DATA

E

ADDRESS

28

37

33

34

35

36