10

Jan, 2008

Document Control #ML0022 Rev 2.1

STK14CA8

MODE SELECTION

E

W

G

Mode

I/O

Power

Notes

H

X

X

X

Not Selected

Output High Z

Standby

L

H

L

X

Read SRAM

Output Data

Active

L

L

X

X

Write SRAM

Input Data

Active

L

H

L

0x04E38

0x0B1C7

0x083E0

0x07C1F

0x0703F

0x08B45

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Read SRAM

AutoStore Disable

Output Data

Output Data

Output Data

Output Data

Output Data

Output Data

Active

q,r,s

L

H

L

0x04E38

0x0B1C7

0x083E0

0x07C1F

0x0703F

0x04B46

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Read SRAM

AutoStore Enable

Output Data

Output Data

Output Data

Output Data

Output Data

Output Data

Active

q,r,s

L

H

L

0x04E38

0x0B1C7

0x083E0

0x07C1F

0x0703F

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Output Data

Output Data

Output Data

Output Data

Output Data

Active

q,r,s

0x08FC0

Nonvolatile Store

Output High Z

L

H

L

0x04E38

0x0B1C7

0x083E0

0x07C1F

0x0703F

0x04C63

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Nonvolatile Recall

Output Data

Output Data

Output Data

Output Data

Output Data

Output High Z

Active

q,r,s

Notes

q: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.

r: While there are 17 addresses on the STK14CA8, only the lower 16 are used to control software modes

s: I/O state depends on the state of G. The I/O table shown assumes G low