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ST20-GP1 データシート(PDF) 9 Page - STMicroelectronics |
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ST20-GP1 データシート(HTML) 9 Page - STMicroelectronics |
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9 / 116 page  ST20-GP1 9/116 ® Memory subsystem The ST20-GP1 on-chip memory system provides 130 Mbytes/s internal data bandwidth, supporting pipelined 2-cycle internal memory access at 30 ns cycle times. The ST20-GP1 memory system consists of SRAM and a programmable memory interface. The programmable memory interface is also referred to as an external memory interface (EMI). The ST20-GP1 uses 8 or 16-bit external RAM, 8 or 16-bit ROM, and supports an address width of 20 bits. The ST20-GP1 product has 4 Kbytes of on-chip SRAM. The advantage of this is the ability to store time critical code on chip, for instance interrupt routines, software kernels or device drivers, and even frequently used data. The ST20-GP1 memory interface controls the movement of data between the ST20-GP1 and off- chip memory. It is designed to support memory subsystems without any external support logic and is programmable to support a wide range of memory types. Memory is divided into 4 banks which can each have different memory characteristics and each bank can access up to 1 Mbyte of external memory. The normal memory provision in a simple GPS receiver is a single 128K x 8-bit SRAM (55 or 70 ns access time), and a single 64K x 16-bit ROM or Flash ROM (70, 90 or 100 ns access time). The ST20-GP1 can support up to 1 Mbyte of SRAM plus 1 Mbyte of ROM, enabling additional applications to be loaded if required. Low power controller, real time clock and watchdog timer The ST20-GP1 has power-down capabilities configurable in software. When powered down, a timer can be used as an alarm, re-activating the CPU after a programmed delay. This is suitable for ultra low power or solar powered applications such as container tracking, railway truck tracking, or marine navigation buoys that must check they are on station at intervals. The timer can also be used to provide a watchdog function, resetting the system if it times out. The real time clock/calendar function is provided by a 64-bit binary counter running continuously from the low-power clock (nominally 32768 Hz). The ST20-GP1 is designed for 0.5 micron, 3.3 V CMOS technology and runs at speeds of up to 33 MHz. 3.3 V operation provides reduced power consumption internally and allows the use of low power peripherals. In addition, a power-down mode is available on the ST20-GP1. The different power levels of the ST20-GP1 are listed below. • Operating power — power consumed during functional operation. • Stand-by power — power consumed during little or no activity. The CPU is idle but ready to immediately respond to an interrupt/reschedule. • Power-down — clocks are stopped and power consumption is significantly reduced. Func- tional operation is stalled. Normal functional operation can be resumed from previous state as soon as the clocks are stable. No information is lost during power down as all internal logic is static. • Power to most of the chip removed — only the real time clock supply (RTCVDD) power on. In power-down mode the processor and all peripherals are stopped, including the external memory controller and optionally the PLL. Effectively the internal clock is stopped and functional operation is stalled. On restart the clock is restarted and the chip resumes normal functional operation. |
同様の部品番号 - ST20-GP1 |
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同様の説明 - ST20-GP1 |
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