Figure 15-11. Master Burst RECEIVE after Burst SEND ........................................................................ 379
Figure 15-12. Master Burst SEND after Burst RECEIVE ........................................................................ 380
Figure 15-13. Slave Command Sequence ............................................................................................ 381
Figure 16-1.
Ethernet Controller Block Diagram .................................................................................. 406
Figure 16-2.
Ethernet Controller ......................................................................................................... 406
Figure 16-3.
Ethernet Frame ............................................................................................................. 408
Figure 17-1.
Analog Comparator Module Block Diagram ..................................................................... 450
Figure 17-2.
Structure of Comparator Unit .......................................................................................... 451
Figure 17-3.
Comparator Internal Reference Structure ........................................................................ 452
Figure 18-1.
Pin Connection Diagram ................................................................................................ 462
Figure 21-1.
Load Conditions ............................................................................................................ 480
Figure 21-2.
I2C Timing ..................................................................................................................... 483
Figure 21-3.
External XTLP Oscillator Characteristics ......................................................................... 485
Figure 21-4.
Hibernation Module Timing ............................................................................................. 486
Figure 21-5.
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 487
Figure 21-6.
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 487
Figure 21-7.
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 488
Figure 21-8.
JTAG Test Clock Input Timing ......................................................................................... 489
Figure 21-9.
JTAG Test Access Port (TAP) Timing .............................................................................. 489
Figure 21-10. JTAG TRST Timing ........................................................................................................ 489
Figure 21-11. External Reset Timing (RST) .......................................................................................... 490
Figure 21-12. Power-On Reset Timing ................................................................................................. 491
Figure 21-13. Brown-Out Reset Timing ................................................................................................ 491
Figure 21-14. Software Reset Timing ................................................................................................... 491
Figure 21-15. Watchdog Reset Timing ................................................................................................. 491
Figure 22-1.
100-Pin LQFP Package .................................................................................................. 492
9
October 08, 2007
Preliminary
LM3S6938 Microcontroller