13.5
Register Descriptions .............................................................................................................. 300
14
Synchronous Serial Interface (SSI) ................................................................................ 334
14.1
Block Diagram ........................................................................................................................ 334
14.2
Functional Description ............................................................................................................. 334
14.2.1 Bit Rate Generation ................................................................................................................. 335
14.2.2 FIFO Operation ....................................................................................................................... 335
14.2.3 Interrupts ................................................................................................................................ 335
14.2.4 Frame Formats ....................................................................................................................... 336
14.3
Initialization and Configuration ................................................................................................. 343
14.4
Register Map .......................................................................................................................... 344
14.5
Register Descriptions .............................................................................................................. 345
15
Controller Area Network (CAN) Module ......................................................................... 371
15.1
Controller Area Network Overview ............................................................................................ 371
15.2
Controller Area Network Features ............................................................................................ 371
15.3
Controller Area Network Block Diagram .................................................................................... 372
15.4
Controller Area Network Functional Description ......................................................................... 373
15.4.1 Initialization ............................................................................................................................. 373
15.4.2 Operation ............................................................................................................................... 374
15.4.3 Transmitting Message Objects ................................................................................................. 374
15.4.4 Configuring a Transmit Message Object .................................................................................... 374
15.4.5 Updating a Transmit Message Object ....................................................................................... 375
15.4.6 Accepting Received Message Objects ...................................................................................... 375
15.4.7 Receiving a Data Frame .......................................................................................................... 376
15.4.8 Receiving a Remote Frame ...................................................................................................... 376
15.4.9 Receive/Transmit Priority ......................................................................................................... 376
15.4.10 Configuring a Receive Message Object .................................................................................... 376
15.4.11 Handling of Received Message Objects .................................................................................... 377
15.4.12 Handling of Interrupts .............................................................................................................. 377
15.4.13 Bit Timing Configuration Error Considerations ........................................................................... 378
15.4.14 Bit Time and Bit Rate ............................................................................................................... 378
15.4.15 Calculating the Bit Timing Parameters ...................................................................................... 380
15.5
Controller Area Network Register Map ...................................................................................... 382
15.6
Register Descriptions .............................................................................................................. 384
16
Ethernet Controller .......................................................................................................... 412
16.1
Block Diagram ........................................................................................................................ 413
16.2
Functional Description ............................................................................................................. 413
16.2.1 Internal MII Operation .............................................................................................................. 413
16.2.2 PHY Configuration/Operation ................................................................................................... 414
16.2.3 MAC Configuration/Operation .................................................................................................. 415
16.2.4 Interrupts ................................................................................................................................ 417
16.3
Initialization and Configuration ................................................................................................. 418
16.4
Ethernet Register Map ............................................................................................................. 418
16.5
Ethernet MAC Register Descriptions ......................................................................................... 420
16.6
MII Management Register Descriptions ..................................................................................... 437
17
Analog Comparator ......................................................................................................... 456
17.1
Block Diagram ........................................................................................................................ 456
17.2
Functional Description ............................................................................................................. 456
October 01, 2007
6
Preliminary
Table of Contents