List of Figures
Figure 1-1.
Stellaris
® 600 Series High-Level Block Diagram ................................................................ 26
Figure 1-2.
LM3S601 Controller System-Level Block Diagram ............................................................. 33
Figure 2-1.
CPU Block Diagram ......................................................................................................... 35
Figure 2-2.
TPIU Block Diagram ........................................................................................................ 36
Figure 5-1.
JTAG Module Block Diagram ............................................................................................ 45
Figure 5-2.
Test Access Port State Machine ....................................................................................... 48
Figure 5-3.
IDCODE Register Format ................................................................................................. 52
Figure 5-4.
BYPASS Register Format ................................................................................................ 52
Figure 5-5.
Boundary Scan Register Format ....................................................................................... 53
Figure 6-1.
External Circuitry to Extend Reset .................................................................................... 55
Figure 6-2.
Main Clock Tree .............................................................................................................. 58
Figure 7-1.
Flash Block Diagram ...................................................................................................... 113
Figure 8-1.
GPIO Module Block Diagram .......................................................................................... 130
Figure 8-2.
GPIO Port Block Diagram ............................................................................................... 131
Figure 8-3.
GPIODATA Write Example ............................................................................................. 132
Figure 8-4.
GPIODATA Read Example ............................................................................................. 132
Figure 9-1.
GPTM Module Block Diagram ........................................................................................ 169
Figure 9-2.
16-Bit Input Edge Count Mode Example .......................................................................... 173
Figure 9-3.
16-Bit Input Edge Time Mode Example ........................................................................... 174
Figure 9-4.
16-Bit PWM Mode Example ............................................................................................ 175
Figure 10-1.
WDT Module Block Diagram .......................................................................................... 204
Figure 11-1.
UART Module Block Diagram ......................................................................................... 228
Figure 11-2.
UART Character Frame ................................................................................................. 229
Figure 12-1.
SSI Module Block Diagram ............................................................................................. 265
Figure 12-2.
TI Synchronous Serial Frame Format (Single Transfer) .................................................... 267
Figure 12-3.
TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 268
Figure 12-4.
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 269
Figure 12-5.
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 269
Figure 12-6.
Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 270
Figure 12-7.
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 271
Figure 12-8.
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 271
Figure 12-9.
Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 272
Figure 12-10. MICROWIRE Frame Format (Single Frame) .................................................................... 273
Figure 12-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 274
Figure 12-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 274
Figure 13-1.
I2C Block Diagram ......................................................................................................... 302
Figure 13-2.
I2C Bus Configuration .................................................................................................... 303
Figure 13-3.
START and STOP Conditions ......................................................................................... 303
Figure 13-4.
Complete Data Transfer with a 7-Bit Address ................................................................... 304
Figure 13-5.
R/S Bit in First Byte ........................................................................................................ 304
Figure 13-6.
Data Validity During Bit Transfer on the I2C Bus ............................................................... 304
Figure 13-7.
Master Single SEND ...................................................................................................... 307
Figure 13-8.
Master Single RECEIVE ................................................................................................. 308
Figure 13-9.
Master Burst SEND ....................................................................................................... 309
Figure 13-10. Master Burst RECEIVE .................................................................................................. 310
October 01, 2007
8
Preliminary
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