ST6373J3B1 datasheet(10/64 Pages) STMICROELECTRONICS

部品番号	ST6373J3B1

部品情報	8-BIT ROM/OTP/EPROM MCUs FOR DIGITALLY CONTROLLED MULTISYNC/MULTISTANDARD MONITORS

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ST6373

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MEMORY SPACES (Cont’d)

1.3.3 Data Space

The ST6 Core instruction set operates on a specif-

ic space, referred to as the Data Space, which

contains all the data necessary for the program.

Figure 5. Data Space

The Data Space allows the addressing of RAM

(192 bytes), EEPROM (384 bytes plus 128 bytes

for the DDC SPI), ST6 Core and peripheral regis-

ters, as well as read-only data such as constants

and look-up tables.

*) These registers contain write only bits, in which

case the bit operation instructions are not possi-

ble.

DATA RAM/EEP ROM

BANK AREA

000h

03Fh

DATA ROM

WIND OW AREA

040h

07Fh

X REGISTER

080h

Y REGISTER

081h

V REGISTER

082h

W REGISTER

083h

DATA RAM

084h

0BFh

PORT A DATA REGISTER

0C0h

PORT B DATA REGISTER

0C1h

PORT C DATA REGISTE R

0C2h

RESERVED

0C3h

PORT A DIRECT ION REGISTE R

0C4h

PORT B DIRECT ION REGISTE R

0C5h

PORT C DIRECTION REGISTER

0C6h

RESERVED

0C7h

INTERRUPT OPTIO N REGISTER

0C8h

DATA ROM WINDO W REGISTE R

0C9h

PROGRAM ROM PAGE REGIS TER

0CAh

*)

I C SPI DATA REGISTER

0CBh

DDC SPI DATA REGISTE R

0CCh

PORT A OPTION REGISTER

0CDh

PORT B OPTION REGISTER

0CEh

RESERVED

0CFh

ADC RESULT REGIS TER

0D0h

ADC CONTROL REGISTER

0D1h*)

TIMER 1 PRESC ALER REGISTER

0D2h

TIMER 1 COUNTER REGISTE R

0D3h

TIMER 1 STATUS /CONTROL REGISTER

0D4h

TIMER 2 PRESC ALER REGISTER

0D5h

TIMER 2 COUNTER REGISTE R

0D7h

WATCHD OG REGISTER

0D8h

MIRROR REGISTER

0D9h

TIMER 3 PRESCALE R REGISTER

0DAh

TIMER 3 COUNTER REGISTER

0DBh

TIMER 3 STAT US/CONTROL REGISTER

0DCh

EVENT COUNTER DATA REGISTER 1

0DDh

EVENT COUNTER DATA REGISTER 2

0DEh*)

SYNC PROCESSOR CONTR OL REGISTE R

0DFh

*)

D/A 0/4 DATA CONTROL REGIS TER

0E0h*)

D/A 1/5 DATA CONTROL REGIS TER

0E1h*)

D/A 2/6 DATA CONTROL REGIS TER

0E2h*)

D/A 3/7 DATA CONTROL REGIS TER

0E3h*)

D/A 8 DATA CONTROL REGISTER

0E4h*)

I C SPI CONTROL REGISTE R 1

0E5h*)

I C SPI CONTROL REGISTE R 2

0E6h*)

D/A BANK REGISTER

0E7h

DATA RAM BANK REGIS TER

0E8h

DDC EEPROM CONTROL REGISTER

0E9h

EEPROM CONTROL REGISTER

0EAh

DDC SPI CONTRO L REGISTER 1

0EBh

DDC SPI CONTRO L REGISTER 2

0ECh

NMI/PWRI N/VSYNC INTERRU PT REGIST ER

0EDh

HDA DATA REGIS TER 1

0EEh*)

HDA DATA REGIS TER 2

0EFh

*)

PERIOD COUNTER DATA REGISTER

0F0h

PERIOD COUNTER 1 AND BLANK CTRL REG.

0F1h*)

AUTO-COU NTER REGIS TER

0F2h

SCL LATCH AND DDC2B ADDRESS CTRL REG.

0F3h*)

XOR REGIST ER

0F4h

RESERVE D

0F5h

0FEh

ACCUMULATOR

0FFh

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