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データシートサーチシステム |
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データシートサーチシステム |
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ST75C520 データシート(PDF) 3 Page - STMicroelectronics |
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ST75C520 データシート(HTML) 3 Page - STMicroelectronics |
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3 / 45 page  1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 38 39 40 41 42 43 44 45 46 47 48 33 34 35 36 37 AGNDT RXA2 RXA1 AGNDR EXTAL XTAL CLKOUT HALT RESET SCOUT BOS EOS SA0 SA1 SA2 SA3 SA4 SA5 SA6 GND SD0 SD1 SD2 SD3 SD4 SD5 SD6 VCM VREFP VREFN AV DD VDD I - PIN DESCRIPTION I.1 - Pin Connections I.2 - Host Interface The exchanges with the control processor proceed through a 64 Bytes DUAL port RAM shared between the ST75C520 and the Host. The signals associated with this interface are : Pin Name Type Description SD0..SD7 I/O System Data Bus. 8-bit data bus used for asynchronous exchanges between the ST75C520 and the Host through the dual port RAM. High impedance when exchanges are not active. SA0..SA6 I System Address Bus. 7-bit address bus for dual port RAM. SDS (SRD) I System Data Strobe. Active low. Synchronizes all the exchanges. In Motorola mode initiates the exchange, active low. In Intel mode initiates a read exchange, active low. SR/W (SWR) I System Read/Write. In Motorola mode defines the type of exchange read/write. In Intel mode initiates a write exchange, active low. SCS I System Chip Select. Active low. SDTACK OD System Bus Data Acknowledge. Active low. Open drain. SINTR OD System Interrupt Request. Active low. This signal is asserted by the ST75C520 and negated by the host. Open drain. RESET I Reset. Active low. RING I Ring Detect Signal. Active low. INT/MOT I Select Intel/Motorola Interface. ST75C520 3/45 |
同様の部品番号 - ST75C520 |
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同様の説明 - ST75C520 |
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