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STA304 データシート(PDF) 8 Page - STMicroelectronics |
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STA304 データシート(HTML) 8 Page - STMicroelectronics |
8 / 30 page STA304 8/30 3.0 I2S INPUT INTERFACE CONFIGURATION In order to configure the I2S input interface the Configuration Register B (CRB) can be used. Using the 3 I2SI_Align_x bits one of 6 configuration mode can be selected. Following is a table describing each one of them. By default standard I2S input interface slave is provided (mode 1 in bits 0,1,2 of register CRB, I2S_BICK_Pol = 1 and I2SI_LRCK_Pol = 0 with some register) 3.1 Switching characteristics (10 pf load; Fsm=32 KHz to 96KHz): Figure 2. MODE # of SLOTS W. LENGHT ALIGNMENT DELAY SLOT NOTES 0 32 24 Left No 1 32 24 Left Yes 2 32 16 Right No MSb first only 3 32 24 Right No 4 24 24 Left No Slave only 5 Not valid Not valid Not valid Not valid Reserved, do not use. 6 24 16 Right No MSb first only. Slave only 7 24 24 Right No Slave only BICKI frequency (master mode): (slave mode): 3.072MHz Max 6.4 MHz BICKI pulse width low (T0) (slave mode): min 40 ns. BICKI pulse width high (T1) (slave mode): min 40 ns. BICKI active to LRCKI edge delay (T2): min 20 ns. BICKI active to LRCKI edge setup (T3): min 20 ns. SDI valid to BICKI active setup (T4): min 20 ns. BICKI active to SDI hold time (T5): min 20 ns. BICKI falling to LRCKI edge (T6) (master mode): min 3 ns; max 9 ns. T2 T3 T0 T1 T5 T4 T6 D00AU1244 LRCKI BICKI SDI |
同様の部品番号 - STA304 |
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同様の説明 - STA304 |
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