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STCL132KRDEAW89 データシート(PDF) 7 Page - STMicroelectronics |
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STCL132KRDEAW89 データシート(HTML) 7 Page - STMicroelectronics |
7 / 20 page STCL132K Operation 7/20 3 Operation Use of the STCL132K silicon oscillator device is very simple. Once power is applied to VCC pin, a CMOS-compatible square wave output signal is provided on the FOUT output pin (in active mode the Chip Enable (CE) input pin must be at a logic high level). 3.1 Chip enable This feature allows the user to stop the clock and significantly reduce the current consumption when the application is put into power saving mode. When used to clock the microprocessor in place of a crystal, the need for chip enable input stems from a difference in the way microprocessors normally disable their clock. In the case of a crystal or ceramic resonator, when going into power saving mode, the processor simply opens the internal Xtal inverter feedback which results in stopping the crystal oscillations; however in the case of the silicon oscillators this would not work and the oscillator would continue to run. So in order to use this feature, one of the microprocessor's output pins must be configured to control the silicon oscillator's Chip Enable (CE) input, see typical application circuit diagram in Figure 2. 3.2 Transition to disable At the moment when the Chip Enable (CE) input goes low, the oscillator's output FOUT will immediately go low; then during the disable period the output remains low. Note: For advanced microprocessor applications, other disable modes can be made available as a product option (FOUT completes the last clock period, and then remains low or provides 32 additional cycles before going low to allow the processor to complete the pipelined instructions, etc.). Also, a product option with output in a high-impedance state to allow the system to alternate between several oscillators connected in parallel can be made available. Contact local ST sales office for availability. 3.3 Fast startup and stable wakeup from disable The total startup time until oscillations internally stabilize and remain within specifications is typically 90 µs, i.e. shorter than duration of the first three periods of the generated output signal, see Section 5: DC and AC parameters. This means that 90 µs after power-on or wakeup from disable a first valid period of the output signal occurs on the FOUT pin and is within the specified frequency and duty cycle range (in the meantime the output remains low). This is in comparison to typically milliseconds for crystal oscillators. |
同様の部品番号 - STCL132KRDEAW89 |
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同様の説明 - STCL132KRDEAW89 |
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