74VHC273

2/14

Figure 2: Input Equivalent Circuit

Table 2: Pin Description

Table 3: Truth Table

X : Don’t Care

Figure 3: Logic Diagram

This logic diagram has not be used to estimate propagation delays

PIN N°

SYMBOL

NAME AND FUNCTION

1CLEAR

Asynchronous Master

Reset (Active LOW)

2, 5, 6, 9, 12,

15, 16,19

Q0 to Q7

Flip-Flop Outputs

3, 4, 7, 8, 13,

14, 17, 18

D0 to D7

Data Inputs

11

CLOCK

Clock Input (LOW-to-HIGH

Edge Triggered)

10

GND

Ground (0V)

20

Positive Supply Voltage

INPUTS

OUTPUT

FUNCTION

CLEAR

DB

Q

L

X

X

L

CLEAR

HL

L

HH

H

HX

NO CHANGE