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TDA7342EQ2N データシート(PDF) 11 Page - STMicroelectronics |
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TDA7342EQ2N データシート(HTML) 11 Page - STMicroelectronics |
11 / 21 page TDA7342EQ2N I2C bus interface 11/21 4 I2C bus interface Data transmission from microprocessor to the TDA7342EQ2N and viceversa takes place thru the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be externally connected). 4.1 Data Validity As shown in Figure 3, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. 4.2 Start and Stop Conditions As shown in Figure 5 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP conditions must be sent before each START condition. 4.3 Byte Format Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. 4.4 Acknowledge The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see Figure 5). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. 4.5 Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the µP can use a simplier transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking and decreases the noise immunity. |
同様の部品番号 - TDA7342EQ2N |
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同様の説明 - TDA7342EQ2N |
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