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LM3S600-IQC25-A2T データシート(PDF) 7 Page - Bookham, Inc. |
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LM3S600-IQC25-A2T データシート(HTML) 7 Page - Bookham, Inc. |
7 / 378 page List of Figures Figure 1-1. Stellaris ® 600 Series High-Level Block Diagram ................................................................ 22 Figure 2-1. CPU Block Diagram ......................................................................................................... 29 Figure 2-2. TPIU Block Diagram ........................................................................................................ 30 Figure 5-1. JTAG Module Block Diagram ............................................................................................ 39 Figure 5-2. Test Access Port State Machine ....................................................................................... 42 Figure 5-3. IDCODE Register Format ................................................................................................. 46 Figure 5-4. BYPASS Register Format ................................................................................................ 46 Figure 5-5. Boundary Scan Register Format ....................................................................................... 47 Figure 6-1. External Circuitry to Extend Reset .................................................................................... 49 Figure 6-2. Main Clock Tree .............................................................................................................. 52 Figure 7-1. Flash Block Diagram ...................................................................................................... 103 Figure 8-1. GPIO Port Block Diagram ............................................................................................... 120 Figure 8-2. GPIODATA Write Example ............................................................................................. 121 Figure 8-3. GPIODATA Read Example ............................................................................................. 121 Figure 9-1. GPTM Module Block Diagram ........................................................................................ 158 Figure 9-2. 16-Bit Input Edge Count Mode Example .......................................................................... 162 Figure 9-3. 16-Bit Input Edge Time Mode Example ........................................................................... 163 Figure 9-4. 16-Bit PWM Mode Example ............................................................................................ 164 Figure 10-1. WDT Module Block Diagram .......................................................................................... 193 Figure 11-1. UART Module Block Diagram ......................................................................................... 217 Figure 11-2. UART Character Frame ................................................................................................. 218 Figure 12-1. SSI Module Block Diagram ............................................................................................. 254 Figure 12-2. TI Synchronous Serial Frame Format (Single Transfer) .................................................... 256 Figure 12-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 257 Figure 12-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 258 Figure 12-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 258 Figure 12-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 259 Figure 12-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 260 Figure 12-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 260 Figure 12-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 261 Figure 12-10. MICROWIRE Frame Format (Single Frame) .................................................................... 262 Figure 12-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 263 Figure 12-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 263 Figure 13-1. I2C Block Diagram ......................................................................................................... 291 Figure 13-2. I2C Bus Configuration .................................................................................................... 292 Figure 13-3. START and STOP Conditions ......................................................................................... 292 Figure 13-4. Complete Data Transfer with a 7-Bit Address ................................................................... 293 Figure 13-5. R/S Bit in First Byte ........................................................................................................ 293 Figure 13-6. Data Validity During Bit Transfer on the I2C Bus ............................................................... 293 Figure 13-7. Master Single SEND ...................................................................................................... 296 Figure 13-8. Master Single RECEIVE ................................................................................................. 297 Figure 13-9. Master Burst SEND ....................................................................................................... 298 Figure 13-10. Master Burst RECEIVE .................................................................................................. 299 Figure 13-11. Master Burst RECEIVE after Burst SEND ........................................................................ 300 Figure 13-12. Master Burst SEND after Burst RECEIVE ........................................................................ 301 7 October 01, 2007 Preliminary LM3S600 Microcontroller |
同様の部品番号 - LM3S600-IQC25-A2T |
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同様の説明 - LM3S600-IQC25-A2T |
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