STPCC5HEBI datasheet(9/93 Pages) STMICROELECTRONICS

部品番号	STPCC5HEBI

部品情報	X86 Core PC Compatible Information Appliance System-on-Chip

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GENERAL DESCRIPTION

Release 1.5 - January 29, 2002

9/93

1.8. CLOCK TREE

The STPC Atlas integrates many features and

generates all its clocks from a single 14MHz

oscillator. This results in multiple clock domains as

described in Figure 1-2.

The speed of the PLLs is either fixed (DEVCLK),

either programmable by strap option (HCLK)

either programmable by software (DCLK, MCLK).

When in synchronized mode, MCLK speed is fixed

to HCLKO speed and HCLKI is generated from

MCLKI.

Figure 1-2. STPC Consumer-II clock architecture

IPC

SDRAM controller

North Bridge

14.31818 MHz

XTALO

XTALI

OSC14M

ISACLK

1/4

DEVCLK

(24MHz)

PLL

(14MHz)

1/2

HCLK

PLL

PCICLKI

PCICLKO

South Bridge

1/2

1/3

HCLK

DCLK

PLL

MCLK

PLL

DCLK

MCLKI

MCLKO

CRTC,Video,TV

CPU

x1

x2

VCLK

VIP

GE

Local Bus

Host

ISA

HCLKI

HCLKO

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