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AD7280 データシート(PDF) 4 Page - Analog Devices |
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AD7280 データシート(HTML) 4 Page - Analog Devices |
4 / 33 page AD7280 Preliminary Technical Data Rev. PrD | Page 4 of 33 Parameter1 Min Typ Max Unit Test Conditions/Comments POWER DISSIPATION During Conversion 300 mW VDD = 30 V Full Powerdown Mode 120 µW VDD = 30 V 1 Temperature range is −40°C to +105°C. 2 For dc accuracy specifications, the LSB size for cell voltage measurements is (2VREF-1V)/4096, the LSB size for temperature measurements is 2VREF/4096. 3 ADC Unadjusted Error includes the INL of the ADC and the Gain and Offset Errors of the Vin0 to Vin6 input channels. 4 Total Unadjusted Error includes the INL of the ADC and the Gain and Offset Errors of the Vin0 to Vin6 input channels as well as the temperature coefficient of the 2.5V reference. 5 ADC Unadjusted Error includes the INL of the ADC and the Gain and Offset Errors of the VT input channels. 6 Total Unadjusted Error includes the INL of the ADC and the Gain and Offset Errors of the VT input channels as well as the temperature coefficient of the 2.5V reference. 7 This spec outlines the regulator output current which is available for external use, that is, it does not include the regulator current already being used by the AD7280. 8 CB output can be set to 0V or 5V with respect to negative terminal of cell being balanced. 9 CB1 output ramp up time is defined from the rising edge of the CS command until the CB output exceeds 4V with respect to negative terminal of cell being balanced. 10 CB1 output ramp down time is defined from the falling edge of the CS command until the CB output falls below 50mV with respect to negative terminal of cell being balanced. This specification is defined from the falling edge of CS as any CB outputs which on are switched off for the duration of a CS low pulse and will be switched back on following the rising edge of that CS pulse. 11 CB2 to CB6 output ramp up time is defined from the rising edge of the CS command until the CB output exceeds 4V with respect to negative terminal of cell being balanced. 12 CB2 to CB6 output ramp down time is defined from the falling edge of the CS command until the CB output falls below 50mV with respect to negative terminal of cell being balanced. This specification is defined from the falling edge of CS as any CB outputs which on are switched off for the duration of a CS low pulse and will be switched back on following the rising edge of that CS pulse. TIMING SPECIFICATIONS VDD = 7.5 V to 30 V, VSS = 0 V, DVCC = AVCC = VREG, VDRIVE = 2.7 V to 5.25 V, TA = -40oC to 105oC, unless otherwise noted.1 Table 2. Limit at TMIN, TMAX Parameter 2.7 V ≤ VDRIVE < 4.75 V 4.75 V ≤ VDRIVE ≤ 5.25 V Unit Test Conditions/Comments tCONV 610 610 ns max ADC Conversion time tDELAY 50 50 ns max Propogation delay between adjacent parts on the Daisy Chain fSCLK 10 10 kHz min Frequency of serial read clock 1 1 MHz max tQUIET 200 200 ns min Minimum quiet time required between the end of serial read and the start of the next conversion t1 10 10 ns min Minimum CONVST low pulse t2 10 10 ns min CS falling edge to SCLK rising edge t3 10 10 ns max Delay from CS falling edge until SDO is three-state disabled t4 5 5 ns min SDI setup time prior to SCLK falling edge t5 3 3 ns min SDI hold time after SCLK falling edge t62 20 14 ns max Data access time after SCLK falling edge t7 7 7 ns min SCLK to data valid hold time t8 0.3 × tSCLK 0.3 × tSCLK ns min SCLK high pulse width t9 0.3 × tSCLK 0.3 × tSCLK ns min SCLK low pulse width t10 10 10 ns min CS rising edge to SCLK rising edge t11 10 10 ns max CS rising edge to SDO high impedance 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V. All timing specifications given are with a 25 pF load capacitance. 2 The time required for the output to cross 0.4 V or 2.4 V. |
同様の部品番号 - AD7280 |
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同様の説明 - AD7280 |
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