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AD7280 データシート(PDF) 9 Page - Analog Devices |
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AD7280 データシート(HTML) 9 Page - Analog Devices |
9 / 33 page Preliminary Technical Data AD7280 Rev. PrD | Page 9 of 33 TERMINOLOGY Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Integral Nonlinearity This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale (a point 1 LSB below the first code transition) and full scale (a point 1 LSB above the last code transition). Offset Code Error This applies to straight binary output coding. It is the deviation of the first code transition (00 ... 000) to (00 ... 001) from the ideal, that is, AGND + 1 LSB. Gain Error This applies to straight binary output coding. It is the deviation of the last code transition (111 ... 110) to (111 ... 111) from the ideal (that is, 4 × VREF − 1 LSB, 2 × VREF − 1 LSB, VREF − 1 LSB) after adjusting for the offset error. ADC Unadjusted Error ADC Unadjusted Error includes integral nonlinearity errors, offset and gain errors of the ADC and measurement channel. Total Unadjusted Error (TUE) This is the maximum deviation of the output code from the ideal. Total Unadjusted Error includes integral nonlinearity errors, offset and gain errors and reference drift. Offset Error Match This is the difference in zero code error across all 6 channels. Gain Error Match The difference in gain error across all 6 channels. Track-and-Hold Acquisition Time The track-and-hold amplifier returns to track mode at the end of a conversion. Track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ±½ LSB, after the end of conversion. Common Mode Rejection Ration (CMRR) CMRR is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV sine wave applied to the common-mode voltage of the Vin(n) and Vin(n-1) frequency, fS, as CMRR (dB) = 10 log (Pf/PfS) where Pf is the power at frequency f in the ADC output, and PfS is the power at frequency fS in the ADC output. Power Supply Rejection Ration (PSRR) Variations in power supply affect the full-scale transition but not the converter’s linearity. PSRR is the maximum change in the full-scale transition point due to a change in power supply voltage from the nominal value. Reference Voltage Temperature Coefficient Reference voltage temperature coefficient is derived from the maximum and minimum reference output voltage (VREF) measured at TMIN, T(25°C), and TMAX. It is expressed in ppm/°C using the following equation: 6 10 ) – ( ) 25 ( ) – ) ) / ( × × ° = ° MIN MAX REF REF REF REF T T V ( V ( V C ppm TCV C Min Max where: VREF(Max) = Maximum VREF at TMIN, T(25°C), or TMAX VREF(Min) = Minimum VREF at TMIN, T(25°C), or TMAX VREF(25°C) = VREF at +25°C TMAX = +85°C TMIN = –40°C Output Voltage Hysteresis Output voltage hysteresis, or thermal hysteresis, is defined as the absolute maximum change of reference output voltage after the device is cycled through temperature from either T_HYS+ = +25°C to TMAX to +25°C T_HYS– = +25°C to TMIN to +25°C It is expressed in ppm using the following equation: 6 10 ) 25 ( ) _ ( ) 25 ( ) ( × ° − ° = C V HYS T V C V ppm V REF REF REF HYS where: VREF(25°C) = VREF at 25°C VREF(T_HYS) = Maximum change of VREF at T_HYS+ or T_HYS–. |
同様の部品番号 - AD7280 |
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同様の説明 - AD7280 |
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