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TDA7319 データシート(PDF) 7 Page - STMicroelectronics |
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TDA7319 データシート(HTML) 7 Page - STMicroelectronics |
7 / 16 page Timing Diagram of I 2CBUS Data Validity on the I 2CBUS I 2C BUS INTERFACE Data transmission from microprocessor to the TDA7319 and viceversa takes place thru the 2 wires I 2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be externally connected). Data Validity As shown in fig. 3, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig.4 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH tran- sition of the SDA line while SCL is HIGH. Byte Format Every byte transferred to the SDA line must con- tain 8 bits. Each byte must be followed by an ac- knowledge bit. The MSB is transferred first. Acknowledge The master ( µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 5). The peripheral (audioprocessor) that ac- knowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the recep- tion of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can gen- erate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audio- processor, the µP can use a simplier transmis- sion: simply it generates the 9th clock pulse with- out checking the slave acknowledging, and then sends the new data. This approach of course is less protected from misworking and decreases the noise immunity. Acknowledge on the I 2CBUS TDA7319 7/16 |
同様の部品番号 - TDA7319 |
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同様の説明 - TDA7319 |
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