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AD7682BCPZ データシート(PDF) 6 Page - Analog Devices |
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AD7682BCPZ データシート(HTML) 6 Page - Analog Devices |
6 / 28 page AD7682/AD7689 Rev. 0 | Page 6 of 28 TIMING SPECIFICATIONS VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, all specifications TMIN to TMAX, unless otherwise noted. Table 3. 1 Parameter Symbol Min Typ Max Unit Conversion Time: CNV Rising Edge to Data Available tCONV 2.2 μs Acquisition Time tACQ 1.8 μs Time Between Conversions tCYC 4 μs CNV Pulse Width tCNVH 10 ns Data Write/Read During Conversion tDATA 1.4 μs SCK Period tSCK 15 ns SCK Low Time tSCKL 7 ns SCK High Time tSCKH 7 ns SCK Falling Edge to Data Remains Valid tHSDO 4 ns SCK Falling Edge to Data Valid Delay tDSDO VIO Above 4.5 V 16 ns VIO Above 3 V 17 ns VIO Above 2.7 V 18 ns VIO Above 2.3 V 19 ns CNV Low to SDO D15 MSB Valid tEN VIO Above 4.5 V 15 ns VIO Above 3 V 17 ns VIO Above 2.7 V 18 ns VIO Above 2.3 V 22 ns CNV High or Last SCK Falling Edge to SDO High Impedance tDIS 25 ns CNV Low to SCK Rising Edge tCLSCK 10 ns DIN Valid Setup Time from SCK Falling Edge tSDIN 4 ns DIN Valid Hold Time from SCK Falling Edge tHDIN 4 ns 1 See Figure 2 and Figure 3 for load conditions. |
同様の部品番号 - AD7682BCPZ |
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同様の説明 - AD7682BCPZ |
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