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TSA1203 データシート(PDF) 2 Page - STMicroelectronics |
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TSA1203 データシート(HTML) 2 Page - STMicroelectronics |
2 / 20 page TSA1203 2/20 CONDITIONS AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps, Fin=10.13MHz, Vin@ -1dBFS, VREFP=0.8V, VREFM=0V Tamb = 25°C (unless otherwise specified) DYNAMIC CHARACTERISTICS TIMING CHARACTERISTICS Symbol Parameter Test conditions Min Typ Max Unit SFDR Spurious Free Dynamic Range -68.3 -59.5 dBc SNR Signal to Noise Ratio 60.7 66.1 dB THD Total Harmonics Distortion -66.6 -58 dBc SINAD Signal to Noise and Distortion Ratio 56.5 62.8 dB ENOB Effective Number of Bits 9.1 10.3 bits Symbol Parameter Test conditions Min Typ Max Unit FS Sampling Frequency 0.5 40 MHz DC Clock Duty Cycle 45 50 55 % TC1 Clock pulse width (high) 22.5 25 ns TC2 Clock pulse width (low) 22.5 25 ns Tod Data Output Delay (Clock edge to Data Valid) 10pF load capacitance 9 ns Tpd I Data Pipeline delay for I channel 7 cycles Tpd Q Data Pipeline delay for Q channel 7.5 cycles Ton Falling edge of OEB to digital output valid data 1 ns Toff Rising edge of OEB to digital output tri-state 1 ns |
同様の部品番号 - TSA1203 |
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同様の説明 - TSA1203 |
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