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74LVTH244AD データシート(PDF) 3 Page - NXP Semiconductors |
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74LVTH244AD データシート(HTML) 3 Page - NXP Semiconductors |
3 / 15 page 74LVT_LVTH244A_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 3 September 2008 3 of 15 NXP Semiconductors 74LVT244A; 74LVTH244A 3.3 V octal buffer/line driver; 3-state 5. Pinning information 5.1 Pinning 5.2 Pin description (1) The die substrate is attached to this pad using a conductive die attach material. It cannot be used as a supply pin or input. Fig 3. Pin configuration for SO20 and (T)SSOP20 Fig 4. Pin configuration for DHVQFN20 74LVT244A 74LVTH244A 1OE VCC 1A0 2OE 2Y3 1Y0 1A1 2A3 2Y2 1Y1 1A2 2A2 2Y1 1Y2 1A3 2A1 2Y0 1Y3 GND 2A0 001aae510 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 001aah764 74LVT244A 74LVTH244A Transparent top view 1Y3 1A3 2Y0 2A1 2Y1 1Y2 1A2 2A2 2Y2 1Y1 1A1 2A3 2Y3 1Y0 1A0 2OE 9 12 8 13 7 14 6 15 5 16 4 17 3 18 2 19 terminal 1 index area GND(1) Table 2. Pin description Symbol Pin Description 1OE, 2OE 1, 19 output enable input (active low) 1A0, 1A1, 1A2, 1A3 2, 4, 6, 8 data input 2Y0, 2Y1, 2Y2, 2Y3 9, 7, 5, 3 data output GND 10 ground (0 V) 2A0, 2A1, 2A2, 2A3 11, 13, 15, 17 data input 1Y0, 1Y1, 1Y2, 1Y3, 18, 16, 14, 12 data output VCC 20 supply voltage |
同様の部品番号 - 74LVTH244AD |
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同様の説明 - 74LVTH244AD |
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