CS5464_07 datasheet(11/46 Pages) CIRRUS

部品番号	CS5464

部品情報	Three-channel, Single-phase Power/Energy IC

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メーカー	CIRRUS [Cirrus Logic]

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CS5464

DS682F1

11

SWITCHING CHARACTERISTICS

• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.

• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.

• VA+ = 5 V ±5% VD+ = 3.3 V ±5% or 5 V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.

• Logic Levels: Logic 0 = 0 V, Logic 1 = VD+.

Notes: 17. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.

18. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an

external clock source.

Parameter

Symbol

Min

Typ

Max

Unit

Rise Times

(Note 17)

Any Digital Output

trise

-

50

1.0

-

µs

ns

Fall Times

(Note 17)

Any Digital Output

tfall

-

50

1.0

-

µs

ns

Start-up

Oscillator Start-up Time

XTAL = 4.096 MHz (Note 11)

tost

-60-

ms

Serial Port Timing

Serial Clock Frequency

SCLK

-

2

MHz

Serial Clock

Pulse Width High

Pulse Width Low

t1

t2

200

-

ns

SDI Timing

CS Falling to SCLK Rising

t3

50

-

ns

Data Set-up Time Prior to SCLK Rising

t4

50

-

ns

Data Hold Time After SCLK Rising

t5

100

-

ns

SDO Timing

CS Falling to SDO Driving

t6

-20

50

ns

SCLK Falling to New Data Bit (hold time)

t7

-20

50

ns

CS Rising to SDO Hi-Z

t8

-20

50

ns

E2PROM mode Timing

Serial Clock

Pulse Width Low

Pulse Width High

t9

t10

8

DCLK

MODE setup time to RESET Rising

t11

50

ns

RESET rising to CS falling

t12

48

DCLK

CS falling to SCLK rising

t13

100

8

DCLK

SCLK falling to CS rising

t14

16

DCLK

CS rising to driving MODE low

t15

50

ns

SDO setup time to SCLK rising

t16

100

ns

同様の部品番号 - CS5464_07

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