CS5560_08 datasheet(6/32 Pages) CIRRUS

部品番号	CS5560

部品情報	짹2.5 V / 5 V, 50 kSps, 24-bit, High-throughput ?誇 ADC

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メーカー	CIRRUS [Cirrus Logic]

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CS5560

6

DS713PP1

3/25/08

SWITCHING CHARACTERISTICS

TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;

VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%

Input levels: Logic 0 = 0V = Low; Logic 1 = VD+ = High; CL = 15 pF.

7.

BP/UP can be changed coincident CONV falling. BP/UP must remain stable until RDY falls.

8.

If CONV is held low continuously, conversions occur every 320 MCLK cycles.

If RDY is tied to CONV, conversions will occur every 322 MCLKs.

If CONV is operated asynchronously to MCLK, a conversion may take up to 324 MCLKs.

RDY falls at the end of conversion.

9.

RDY will fall when the device is fully operational when coming out of sleep mode.

Parameter

Symbol

Min

Typ

Max

Unit

Master Clock Frequency

Internal Oscillator

External Clock

XIN

fclk

12

0.5

14

16

16.2

MHz

Master Clock Duty Cycle

40

-

60

%

Reset

RST Low Time

tres

1-

-

µs

RST rising to RDY falling

Internal Oscillator

External Clock

twup

-

120

1536

-

µs

MCLKs

Conversion

CONV Pulse Width

tcpw

4-

-

MCLKs

BP/UP setup to CONV falling

(Note 7)

tscn

0-

-

ns

CONV low to start of conversion

tscn

--

2

MCLKs

Perform Single Conversion (CONV high before RDY falling)

tbus

20

-

MCLKs

Conversion Time

(Note 8)

Start of Conversion to RDY falling

tbuh

--

324

MCLKs

Sleep Mode

SLEEP low to low-power state

SLEEP high to device active (Note 9)

tcon

-

50

3083

-

µs

MCLKs

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同様の説明 - CS5560_08

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