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TSC695F データシート(PDF) 11 Page - ATMEL Corporation |
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TSC695F データシート(HTML) 11 Page - ATMEL Corporation |
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11 / 42 page  11 TSC695F 4118J–AERO–08/04 Timers In software debug mode the timers are controlled by a system register bit and the exter- nal pin DEBUG. General Purpose Timer The General Purpose Timer (GPT) provides, in addition to a generalized counter func- tion, a mechanism for setting the step size in which actual time counts are performed. GPT is clocked by the internal system clock. They are possible to program to be either of single-shot type or periodical type and in both cases generate an interrupt when the delay time has elapsed. The current value of the scaler and counter of the GPT can be read. Real Time Clock Timer The only functional differences between the two timers are that the Real Time Clock Timer (RTCT) has an 8-bit scaler (16-bit scaler for GPT) and that the RTCT interrupt has higher priority than the GPT interrupt. RTCT information is available on RTC output pin. Watchdog Timer Setting the external pin IWDE to V CC enables the internal watchdog timer. Otherwise the watchdog function must be externally provided. The watchdog is supplied from a separate external input (WDCLK). After reset, the timer is enabled and starts running with the maximum range. If the timer is not refreshed (reprogrammed) before the counter reaches zero value, an interrupt is sent. Simulta- neo usly, the tim er starts counting a reset time -out period. If the ti mer is not acknowledged before the reset time-out period elapses, a reset is applied to TSC695F. UARTs Two full duplex asynchronous receiver transmitters (UART) are included. In software debug mode the UART’s are controlled by system register bits. The data format of the UART’s is eight bits. It is possible to choose between even or odd parity, or no parity, and between one and two stop bits. The UART’s provide double buff- ering, i.e. each UART consists of a transmitter holding register, a receiver holding register, a transmitter shift register, and a receiver shift register. Each of these registers are 8-bit wide. For each UART a RX and TX Register is provided. The UART’s generate an interrupt each time a byte has been received or a byte has been sent. There is another interrupt to indicate errors. The baud rate of both the UART’s is programmable. The clock is derived either from the system clock or can use the watchdog clock. General Purpose Interface The General Purpose Interface (GPI) is an 8-bit parallel I/O port. Each pin can be config- ured as an input or an output. A falling or rising edge detection is made on each selected GPI inputs. Every input tran- sition on GPI generates an external positive pulse on GPIINT pin of two SYSCLK width. Execution Modes Reset Mode Reset mode is entered when: – The SYSRES input is asserted – Software reset which is caused by the software writing to a Software Reset Register – Watchdog reset which is caused by a Watchdog counter time-out – Error reset which is caused by a hardware parity error |
同様の部品番号 - TSC695F_04 |
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同様の説明 - TSC695F_04 |
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