CDCE62005RGZR datasheet(4/76 Pages) TI

部品番号	CDCE62005RGZR

部品情報	Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

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CDCE62005

SCAS862 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com

PIN FUNCTIONS (continued)

TYPE

DESCRIPTION

NAME

QFN

REF_SEL

31

I

If Auto Reference Select Mode is OFF this Pin acts as External Input Reference Select Pin;

The REF_SEL signal selects one of the two input clocks:

REF_SEL [1]: PRI_IN is selected; REF_SEL [0]: SEC_IN is selected;

The input has an internal 150-k

Ω pull-up resistor if left unconnected it will default to logic level “1”.

If Auto Reference Select Mode in ON this Pin not used.

Power_Down

12

I

Active Low. Power down mode can be activated via this pin. See Table 14 for more details. The

input has an internal 150-k

Ω pull-up resistor if left unconnected it will default to logic level “1”.

SPI_LE has to be HIGH in order for the rising edge of Power_Down signal to load the EEPROM.

SYNC

14

I

Active Low. Sync mode can be activated via this pin. See Table 14 for more details. The input has

an internal 150-k

Ω, pull-up resistor if left unconnected it will default to logic level “1”.

AUX IN

43

I

Auxiliary Input is a single ended input including an on-board oscillator circuit so that a crystal may

be connected.

AUX OUT

13

O

Auxiliary Output LVCMOS level that can be programmed via SPI interface to be driven by Output 2

or Output 3.

PRI REF+

45

I

Universal Input Buffer (LVPECL, LVDS, LVCMOS) positive input for the Primary Reference Clock,

PRI REF–

46

I

Universal Input Buffer (LVPECL, LVDS) negative input for the Primary Reference Clock. In case of

LVCMOS signaling Ground this pin.

SEC REF+

3

I

Universal Input Buffer (LVPECL, LVDS, LVCMOS) positive input for the Secondary Reference

Clock,

SEC REF–

2

I

Universal Input Buffer (LVPECL, LVDS,) negative input for the Secondary Reference Clock. In

case of LVCMOS signaling Ground this pin.

TESTOUTA

30

Analog

Analog Test Point for Use for TI Internal Testing. Pull Down to GND Via a 1k

Ωs Resistor.

REG_CAP1

4

Analog

Capacitor for the internal Regulator. Connect to a 10uF Capacitor (Y5V)

REG_CAP2

38

Analog

Capacitor for the internal Regulator. Connect to a 10uF Capacitor (Y5V)

VBB

48

Analog

Capacitor for the internal termination Voltage. Connect to a 1uF Capacitor (Y5V)

EXT_LFP

40

Analog

External Loop Filter Input Positive

EXT_LFN

41

Analog

External Loop Filter Input Negative.

PLL_LOCK

37

AI/O

Output that indicates PLL Lock Status. See Figure 36.

U0P:U0N

27, 28

O

The Main outputs of CDCE62005 are user definable and can be any combination of up to 5

LVPECL outputs, 5 LVDS outputs or up to 10 LVCMOS outputs. The outputs are selectable via

U1P:U1N:

19, 20

SPI interface. The power-up setting is EEPROM configurable.

U2P:U2N

16,17

U3P:U3N

9, 10

U4P:U4N

6, 7

4

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