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TELCOM SEMICONDUCTOR, INC.

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Auto Zero Phase (AZ)

This phase compensates for errors due to buffer, inte-

grator and comparator offset voltages. During this phase, an

internal feedback loop forces a compensating error voltage

is programmable via the serial port (see also Programming

AZ and INT Phase Duration paragraph of this document).

Input Integrate Phase (INT)

In this phase, a current directly proportional to differen-

phase is directly proportional to the applied differential input

voltage. Input signal polarity (sign bit) is determined at the

end of this phase. Converter resolution and conversion

speed is a function of the duration of the INT phase, which

is programmable by the user via the serial port (see also

Programming AZ and INT Phase Duration paragraph of this

document). The shorter the integration time, the faster the

speed of conversion, but the lower the resolution. Con-

versely, the longer the integration time, the greater the

resolution, but at slower the speed of conversion.

Reference Deintegrate Phase (DINT)

This phase consists of measuring the time for the

integrator output to return (at a rate determined by the

external reference voltage) from its initial voltage to 0V. The

resulting timer data is stored in the output shift register as

converted analog data.

Integrator Output Zero Phase (IZ)

This phase guarantees the integrator output is at zero

volts when the AZ phase is entered so that only true system

offset voltages will be compensated for.

All internal converter timing is derived from the fre-

source must be either an externally provided clock signal, or

an external crystal. If an external clock is used, it must be

remain floating. If a crystal is used, it must be connected

case, the incoming clock frequency is divided by four and the

resulting clock serves as the internal TC530/534 timebase.

APPLICATIONS

Programming the TC530/534

AZ and INT Phase Duration:

These two phases have equal duration determined by

the crystal (or external) frequency and the timer initialization

byte (LOAD VALUE). Timing is selected as follows:

(1) Select Integration Time

Integration time must be picked as a multiple of the

of 33msec, 66msec and 132msec maximize 60Hz

line rejection.

(2) Estimate Crystal Frequency

Crystal frequencies as high as 2MHz are allowed.

Crystal frequency is estimated using:

2(R)

where: R

= Desired Converter Resolution

(in counts)

INT = Integration Time (in seconds)

(3) Calculate LOAD VALUE

1024

The resulting base -10 LOAD VALUE must be converted to

a hexadecimal number, then loaded into the serial port prior

to initiating A/D conversion.

amount of voltage stored on the integrator capacitor during

immediately following INT and terminated when an integra-

tor output zero-crossing is detected. In general, the maxi-

System RESET

The TC530/534 must be forced into the AZ state when

power is first applied. A .01

µF capacitor connected from

used to momentarily drive RESET high for a minimum of

100msec.

Selecting Component Values for the TC530/534

The desired full-scale input voltage and amplifier

The buffer and integrator amplifiers each have a full-

scale current of 20

µA.

follows:

5V PRECISION DATA ACQUISITION

SUBSYSTEMS

TC530

TC534