データシートサーチシステム |
|
TC514CPJ データシート(PDF) 7 Page - TelCom Semiconductor, Inc |
|
TC514CPJ データシート(HTML) 7 Page - TelCom Semiconductor, Inc |
7 / 17 page 3-25 TELCOM SEMICONDUCTOR, INC. 7 6 5 4 3 1 2 8 ∫ 0.01 0.1 1.0 80 70 60 50 40 30 20 t = 0.1 sec LINE FREQUENCY DEVIATION FROM 60 Hz (%) NORMAL MODE REJECTION = 20 LOG DEV = DEVIATION FROM 60 Hz t = INTEGRATION PERIOD SIN 60 t (1 ± ) π DEV 100 DEV 100 60 t (1 ± ) Figure 3. Line Frequency Deviation Figure 4.. Integrating Converter Normal Mode Rejection 30 20 10 0 0.1/T 1/T 10/T INPUT FREQUENCY T = MEASUREMENT PERIOD 1 tINT VIN (t) dt = VREF tDEINT RINT CINT 0 RINT CINT where: VREF = Reference Voltage tINT = Signal Integration time (fixed) tDEINT = Reference Voltage Integration time (variable) For a constant VIN: VIN = VREF tDEINT tINT The dual-slope converter accuracy is unrelated to the integrating resistor and capacitor values as long as they are stable during a measurement cycle. An inherent benefit is noise immunity. Input noise spikes are integrated (averaged to zero) during the integration periods. Integrating ADCs are immune to the large conver- sion errors that plague successive approximation convert- ers in high-noise environments. Integrating converters provide inherent noise rejection with at least a 20dB/decade attenuation rate. Interference signals with frequencies at integral multiples of the integra- tion period are, theoretically, completely removed since the average value of a sine wave of frequency (1/t) averaged over a period (t) is zero. Integrating converters often establish the integration period to reject 50/60Hz line frequency interference signals. The ability to reject such signals is shown by a normal mode rejection plot (Figure 4). Normal mode rejection is limited in practice to 50 to 65dB, since the line frequency can deviate by a few tenths of a percent (Figure 3). TC500/500A/510/514 CONVERTER OPERATION The TC500/500A/510/514 incorporates an Auto zero and Integrator phase in addition to the input signal Integrate and reference Deintegrate phases. The addition of these phases reduce system errors and calibration steps, and shorten overrange recovery time. A typical measurement cycle uses all four phases in the following order: (1) Auto zero (2) Input signal integration (3) Reference deintegration (4) Integrator output zero The internal analog switch status for each of these phases is summarized in Table 1. This table is referenced to the Functional Block Diagram on the first page of this data sheet. Auto-Zero Phase (AZ) During this phase, errors due to buffer, integrator and comparator offset voltages are nulled out by charging CAZ (auto-zero capacitor) with a compensating error voltage. The external input signal is disconnected from the internal circuitry by opening the two SWI switches. The internal input points connect to analog common. The refer- ence capacitor is charged to the reference voltage potential through SWR. A feedback loop, closed around the integrator and comparator, charges the CAZ capacitor with a voltage to compensate for buffer amplifier, integrator and comparator offset voltages. PRECISION ANALOG FRONT ENDS TC500 TC500A TC510 TC514 |
同様の部品番号 - TC514CPJ |
|
同様の説明 - TC514CPJ |
|
|
リンク URL |
プライバシーポリシー |
ALLDATASHEET.JP |
ALLDATASHEETはお客様のビジネスに役立ちますか? [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |