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TC820CPL データシート(PDF) 9 Page - TelCom Semiconductor, Inc |
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TC820CPL データシート(HTML) 9 Page - TelCom Semiconductor, Inc |
9 / 22 page 3-157 TELCOM SEMICONDUCTOR, INC. 7 6 5 4 3 1 2 8 where: VREF = Reference voltage tINT = Integration time tDEINT = Deintegration time For a constant t INT: VIN = VREF 0 tDEINT tINT Accuracy in a dual-slope converter is unrelated to the integrating resistor and capacitor values as long as they are stable during a measurement cycle. An inherent benefit of the dual-slope technique is noise immunity. Noise spikes are integrated or averaged to zero during the integration periods, making integrating ADCs immune to the large conversion errors that plague successive approximation converters in high-noise environments. Interfering signals, with frequency components at multiples of the averaging (integrating) period, will be attenuated (Figure 3). Integrating ADCs commonly operate with the signal integration period set to a multiple of the 50/60Hz power line period. Figure 3. Normal-Mode Rejection of Dual-Slope Converter 30 20 10 0 0.1/T 1/T 10/T INPUT FREQUENCY T = MEASUREMENT PERIOD Analog Section In addition to the basic integrate and deintegrate dual- slope phases discussed above, the TC820 design incorpo- rates a "zero integrator output" phase and an "auto-zero" phase. These additional phases ensure that the integrator starts at 0V (even after a severe overrange conversion), and that all offset voltage errors (buffer amplifier, integrator and comparator) are removed from the conversion. A true digital zero reading is assured without any external adjustments. A complete conversion consists of four distinct phases: (1) Zero Integrator Output (2) Auto-Zero (3) Signal Integrate (4) Reference Deintegrate Zero Integrator Output Phase This phase guarantees that the integrator output is at 0V before the system zero phase is entered, ensuring that the true system offset voltages will be compensated for even after an overrange conversion. The duration of this phase is 500 counts plus the unused deintegrate counts. Auto-Zero Phase During the auto-zero phase, the differential input signal is disconnected from the measurement circuit by opening internal analog switches, and the internal nodes are shorted to Analog Common (0VREF) to establish a zero input condi- tion. Additional analog switches close a feedback loop around the integrator and comparator to permit comparator offset voltage error compensation. A voltage established on CAZ then compensates for internal device offset voltages during the measurement cycle. The auto-zero phase re- sidual is typically 10 µV to 15µV. The auto-zero duration is 1500 counts. Signal Integration Phase Upon completion of the auto-zero phase, the auto-zero loop is opened and the internal differential inputs connect to VIN+ and VIN–. The differential input signal is then integrated for a fixed time period, which is 2000 counts (4000 clock periods). The externally-set clock frequency is divided by two before clocking the internal counters. The integration time period is: tINT = The differential input voltage must be within the device's common-mode range when the converter and measured system share the same power supply common (ground). If the converter and measured system do not share the same power supply common, as in battery-powered applications, VIN– should be tied to analog common. Polarity is determined at the end of signal integration phase. The sign bit is a "true polarity" indication in that signals less than 1 LSB are correctly determined. This allows precision null detection that is limited only by device noise and auto-zero residual offsets. 1 RINT CINT ∫ tINT VIN(t)dt= VREFtDEINT RINT CINT 4000 fOSC TC820 3-3/4 A/D CONVERTER WITH FREQUENCY COUNTER AND LOGIC PROBE |
同様の部品番号 - TC820CPL |
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同様の説明 - TC820CPL |
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