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TC820CPL データシート(PDF) 10 Page - TelCom Semiconductor, Inc |
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TC820CPL データシート(HTML) 10 Page - TelCom Semiconductor, Inc |
10 / 22 page 3-158 TELCOM SEMICONDUCTOR, INC. 3-3/4 A/D CONVERTER WITH FREQUENCY COUNTER AND LOGIC PROBE TC820 Peak Reading Hold The TC820 provides the capability of holding the highest (or peak) reading. Connecting the PK HOLD input to VDD enables the peak hold feature. At the end of each conversion the contents of the TC820 counter is compared to the contents of the display register. If the new reading is higher than the reading being displayed, the higher reading is transferred to the display register. A "higher" reading is defined as the reading with the higher absolute value. The peak reading is held in the display register so the reading will not "droop" or slowly decay with time. The held reading will be retained until a higher reading occurs, the PK HOLD input is disconnected from VDD, or power is removed. The peak signal to be measured must be present during the TC820 signal integrate period. The TC820 does not perform transient peak detection of the analog input signal. However, in many cases, such as measuring temperature or electric motor starting current, the TC820 "acquisition time" will not be a limitation. If true peak detection is required, a simple circuit will suffice. See the applications section for details. The peak reading function is also available when the TC820 is in the frequency counter mode. The counter auto- ranging feature is disabled when peak reading hold is selected. 10:1 Range Change The analog input full-scale range can be changed with the RANGE/FREQ input. Normally, RANGE/FREQ is held low by an internal pulldown. Connecting this pin to VS+ will increase the full-scale voltage by a factor of 10. No external component changes are required. The RANGE/FREQ input operates by changing the integrate period. When RANGE/FREQ is connected to VDD, the signal integration phase of the conversion is reduced by a factor of 10 (i.e., from 2000 counts to 200 counts). For the TC820, the 10:1 range change will result in ±4V full scale. This full-scale range will exceed the common- mode range of the input buffer when operating from a 9V battery. If range changing is required for the TC820, a higher supply voltage can be provided or the input voltage can be divided by 2 externally. Frequency Counter In addition to serving as an analog-to-digital converter, the TC820 internal counter can also function as a frequency counter (Figure 4). In the counter mode, pulses at the RANGE/FREQ input will be counted and displayed. The frequency counter derives its time base from the clock oscillator. The counter time base is: tCOUNT = fOSC 40,000 Reference Integrate (Deintegrate) Phase The reference capacitor, which was charged during the auto-zero phase, is connected to the input of the integrating amplifier. The internal sign logic ensures the polarity of the reference voltage is always connected in the phase opposite to that of the input voltage. This causes the integrator to ramp back to zero at a constant rate determined by the reference potential. The amount of time required (TDEINT) for the integrating amplifier to reach zero is directly proportional to the ampli- tude of the voltage that was put on the integrating capacitor (VINT) during the integration phase: tDEINT = The digital reading displayed by the TC820 is: Digital Count = 2000 System Timing The oscillator frequency is divided by 2 prior to clocking the internal decade counters. The four-phase measurement cycle takes a total of 8000 (4000) counts or 16000 clock pulses. The 8000 count phase is independent of input signal magnitude or polarity. Each phase of the measurement cycle has the following length: Conversion Phase Counts 1) Auto-Zero: 1500 2) Signal Integrate:1,2 2000 3) Reference Integrate: 1 to 4001 4) Integrator Output Zero: 499 to 4499 NOTES: 1. This time period is fixed. The integration period for the TC820 is: tINT (TC820) = = 2000 counts where fOSC is the clock oscillator frequency. 2. Times shown are the RANGE/FREQ at logic low (normal operation). When RANGE/FREQ is logic high, signal integrate times are 200 counts. See "10:1 Range Change" section. RINT CINT VINT VREF V+IN – V–IN VREF Input Overrange When the analog input is greater than full scale, the LCD will display "OL" and the "OVERRANGE" LCD annunciator will be on. 4000 fOSC |
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同様の説明 - TC820CPL |
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