3-82

TELCOM SEMICONDUCTOR, INC.

15-BIT, FAST-INTEGRATING CMOS

ANALOG-TO-DIGITAL CONVERTER

TC850

Figure 2A. Dual-Slope ADC Cycle

Figure 2B. "Fast-Slow" Reference Deintegrate Cycle

additional 6 bits of resolution. The result is 15 bits of

pulses for deintegration. A complete conversion cycle occu-

pies only 1280 clock pulses.

In order to generate "fast-slow" integration phases, two

voltage references are required. The primary reference

mV). To maintain 15-bit linearity, a tolerance of 0.5% for

ANALOG SECTION DESCRIPTION

The TC850 analog section consists of an input buffer

amplifier, integrator amplifier, comparator, and analog

switches. A simplified block diagram is shown in Figure 3.

Conversion Timing

Each conversion consists of three phases: (1) Zero

Integrator, (2) Signal Integrate, and (3) Reference Integrate

(or Deintegrate). Each conversion cycle requires 1280 inter-

nal clock cycles (Figure 4).

Figure 3. Analog Section Simplified Schematic

AUTO

ZERO

0V

INTEGRATOR

OUTPUT

END OF

CONVERSION

REFERENCE

DEINTEGRATE

SIGNAL

INTEGRATE

TIME

AUTO

ZERO

0V

INTEGRATOR

OUTPUT

END OF

CONVERSION

"SLOW" REFERENCE

DEINTEGRATE

(6-BIT RESOLUTION)

"FAST" REFERENCE

DEINTEGRATE

(9-BIT RESOLUTION)

SIGNAL

INTERGRATE

TIME

CREF1

REF1–

RINT

INTIN

INTOUT

CINT

INT

INT

INT

BUFFER*

BUFF

INTEGRATOR*

COMPARATOR*

TO

DIGITAL

SECTION

DE1

(+)

DE

DE

DE

Z1

DE

DE1

(+)

DE1

(–)

DE1

(–)

DE2

(+)

DE2

(–)

DE1

(+)

DE1

(–)

COMMON

C REF1

+

C REF1

–

C REF2

–

C REF2

–

C REF2

REF2+

+

IN

+

IN

–

REF1

+

–

+

–

+

–

TC850

*AUTO-ZEROED

AMPLIFIERS