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TS80C52X2-LCAB データシート(PDF) 11 Page - TEMIC Semiconductors |
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TS80C52X2-LCAB データシート(HTML) 11 Page - TEMIC Semiconductors |
11 / 54 page Rev. B - Jan. 25, 1999 11 Preliminary TS80C52X2 Table 5. AUXR1: Auxiliary Register 1 Reset Value = XXXX XXX0 Not bit addressable Application Software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare, search ...) are well served by using one data pointer as a ’source’ pointer and the other one as a "destination" pointer. 7 6 5 4 3 2 1 0 - - - - - - - DPS Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. 2 - Reserved The value read from this bit is indeterminate. Do not set this bit. 1 - Reserved The value read from this bit is indeterminate. Do not set this bit. 0 DPS Data Pointer Selection Clear to select DPTR0. Set to select DPTR1. |
同様の部品番号 - TS80C52X2-LCAB |
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同様の説明 - TS80C52X2-LCAB |
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