データシートサーチシステム |
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ISL54064 データシート(PDF) 8 Page - Intersil Corporation |
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ISL54064 データシート(HTML) 8 Page - Intersil Corporation |
8 / 15 page 8 FN6582.0 February 25, 2009 Test Circuits and Waveforms Logic input waveform is inverted for switches that have the opposite logic sense. FIGURE 1A. MEASUREMENT POINTS Repeat test for all switches. CL includes fixture and stray capacitance. FIGURE 1B. TEST CIRCUIT FIGURE 1. SWITCHING TIMES FIGURE 2A. MEASUREMENT POINTS FIGURE 2B. TEST CIRCUIT FIGURE 2. CHARGE INJECTION FIGURE 3. OFF-ISOLATION TEST CIRCUIT FIGURE 4. rON TEST CIRCUIT 50% tr < 5ns tf < 5ns tOFF 90% V+ 0V VNO 0V tON LOGIC INPUT SWITCH INPUT SWITCH OUTPUT 90% VOUT V OUT V (NO or NC) R L R L r ON + ------------------------ = SWITCH INPUT LOGIC INPUT VOUT RL CL COM NO OR NC IN 50 Ω 35pF GND V+ C VOUT ΔVOUT ON OFF ON Q = ΔVOUT x CL SWITCH OUTPUT LOGIC INPUT V+ 0V CL VOUT RG VG GND COM NO OR NC V+ C LOGIC INPUT IN Repeat test for all switches. ANALYZER RL SIGNAL GENERATOR V+ C 0V OR V+ NO OR NC COM IN GND Signal direction through switch is reversed, worst case values are recorded. Repeat test for all switches. *50 Ω SOURCE V+ C 0V OR V+ NO OR NC COM IN GND VNX V1 rON = V1/100mA 100mA Repeat test for all switches. ISL54063, ISL54064 |
同様の部品番号 - ISL54064 |
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同様の説明 - ISL54064 |
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