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CD54AC32F3A データシート(PDF) 4 Page - Texas Instruments

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部品番号 CD54AC32F3A
部品情報  Quad 2-Input OR Gate
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メーカー  TI [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI - Texas Instruments

CD54AC32F3A データシート(HTML) 4 Page - Texas Instruments

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Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case)
PARAMETER
SYMBOL
VCC (V)
-40oC TO 85oC
-55oC TO 125oC
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
AC TYPES
Propagation Delay, Input to
Output
tPLH, tPHL
1.5
-
-
108
-
-
119
ns
3.3
(Note 9)
3.4
-
12.1
3.3
-
13.3
ns
5
(Note 10)
2.4
-
8.6
2.4
-
9.5
ns
Input Capacitance
CI
-
-
-10-
-10
pF
Power Dissipation Capacitance
CPD
(Note 11)
-
-
47
-
-
47
-
pF
ACT TYPES
Propagation Delay, Input to
Output
tPHL
tPLH
5
(Note 10)
3.1
-
11
3
-
12.1
ns
Input Capacitance
CI
-
-
-10-
-10
pF
Power Dissipation Capacitance
CPD
(Note 11)
-
-
47
-
-
47
-
pF
NOTES:
8. Limits tested at 100%.
9. 3.3V Min at 3.6V, Max at 3V.
10. 5V Min at 5.5V, Max at 4.5V.
11. CPD is used to determine the dynamic power consumption per gate.
AC: PD = VCC
2 f
i (CPD + CL)
ACT: PD = VCC
2 f
i (CPD + CL) + VCC ∆ICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage.
DUT
OUTPUT
RL (NOTE)
OUTPUT
LOAD
500
CL
50pF
NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.
FIGURE 1. PROPAGATION DELAY TIMES
AC
ACT
Input Level
VCC
3V
Input Switching Voltage, VS
0.5 VCC
1.5V
Output Switching Voltage, VS
0.5 VCC
0.5 VCC
FIGURE 2.
GND
INPUT
LEVEL
tPLH
tr = 3ns
tf = 3ns
90%
VS
10%
tPHL
VS
(A, B)
Y
CD54/74AC32, CD54/74ACT32


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