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TPA6140A2YFFR データシート(PDF) 5 Page - Texas Instruments |
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TPA6140A2YFFR データシート(HTML) 5 Page - Texas Instruments |
5 / 27 page ELECTRICAL CHARACTERISTICS TIMING CHARACTERISTICS SCL SDA tw(H) tw(L) tsu1 th1 TPA6140A2 www.ti.com .................................................................................................................................................................................................. SLOS598 – MARCH 2009 TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PSRR Power supply rejection ratio AVDD = 2.5 V to 5.5 V, inputs grounded, GAIN = 0 dB 90 105 dB CMRR Common-mode rejection ratio HPVDD = 1.3 V to 1.8 V, GAIN = 0 dB 68 dB |IIH| High-level input current AVDD = 2.5 V to 5.5 V, VI = AVDD SCL, SDA 1 µA |IIL| Low-level input current AVDD = 2.5 V to 5.5 V, VI = 0 V SCL, SDA 1 µA ISD Soft shutdown current SW Shutdown mode, VDD = 2.5 V to 5.5 V, SWS bit = 1 1 3 µA AVDD = 3.6 V HPVDD = 1.3 V, Amplifiers active, no load, no 1.2 2.0 input signal AVDD = 3.6 V, POUT = 100 µW into 32 Ω (1), f AUD = 1 kHz 2.5 IDD Total supply current AVDD = 3.6 V, POUT = 500 µW into 32 Ω (1), f AUD = 1 kHz 4.0 mA AVDD = 3.6 V, POUT = 1 mW into 32 Ω (1), f AUD = 1 kHz 6.8 AVDD = 3.6 V, HiZ_L = HiZ_R = HIGH (High output impedance 1.0 2.0 mode) (1) Per channel output power assuming a 10 dB crest factor For I 2C interface signals over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fSCL Frequency, SCL No wait states 400 kHz tW(H) Pulse duration, SCL high 0.6 µs tW(L) Pulse duration, SCL low 1.3 µs tSU1 Setup time, SDA to SCL 100 µs tH1 Hold time, SCL to SDA 10 ns t(BUF) Bus free time between stop and start condition 1.3 µs tSU2 Setup time, SCL to start condition 0.6 µs tH2 Hold time, start condition to SCL 0.6 µs tSU3 Setup time, SCL to stop condition 0.6 µs Figure 1. SCL and SDA Timing Copyright © 2009, Texas Instruments Incorporated 5 Product Folder Link(s): TPA6140A2 |
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