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APPLICATION INFORMATION

OEC

Termination Voltage, V

TT

Reference Voltage, V

REF

C

R

2R

Partial Power Down

Bus-Hold Circuit

SN54GTL16612A, SN74GTL16612A

18-BIT LVTTL-TO-GTL+ UNIVERSAL BUS TRANSCEIVERS

SCES187D – JANUARY 1999 – REVISED JULY 2005

The 'GTL16612A GTL output consists of an improved edge-control circuit that provides optimized rise and fall

times, typically 2.6 ns (20% to 80%), for backplanes under various loading conditions.

Using the definition of slew rate

∆t/∆v = t

comparison, these values are significantly more than those of previous GTL or standard TTL devices, which are

usually about 1 ns/V, or less.

per signal line. There are various voltage regulators that meet these requirements. Depending on the application,

the regulators should be mounted either directly on the backplane or on the daughter boards. It is highly

recommended that ceramic bypass capacitors be used (due to high impedance) at the termination resistors

because several signal lines may be switching simultaneously, causing considerable current fluctuations at the

termination voltage.

R-to-2R ratio and a bypass capacitor (0.01–0.1

µF) as close to the V

backplane.

Device power can be switched off without having to remove the device from the system. This is a partial power

which specifies the maximum input or output leakage current.

Bus hold on A-port inputs (LVTTL side) prevents any unused or floating inputs from damaging the device. To

change the logic state stored by the bus-hold circuit, a current of about 250-300

µA must be overridden. There is

no bus hold on the B port (GTL side). A bus-hold circuit on the GTL side would defeat the purpose of the

open-drain outputs, which take on the high-impedance state to allow the bus to achieve a logic high state via the

pullup resistors.

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