データシートサーチシステム |
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SN74LV273APWRE4 データシート(PDF) 2 Page - Texas Instruments |
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SN74LV273APWRE4 データシート(HTML) 2 Page - Texas Instruments |
2 / 17 page SN54LV273A, SN74LV273A OCTAL DTYPE FLIPFLOPS WITH CLEAR SCLS399J − APRIL 1998 − REVISED APRIL 2005 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description/ordering information (continued) These devices are positive-edge-triggered flip-flops with direct clear (CLR) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. FUNCTION TABLE (each flip-flop) INPUTS OUTPUT CLR CLK D OUTPUT Q L X X L H ↑ HH H ↑ LL H L X Q0 logic diagram (positive logic) CLK 1D 1Q 2D 2Q 3D 3Q 4D 4Q 5D 5Q 6D 6Q 7D 7Q 8D 8Q CLR 1D R C1 1D R C1 1D R C1 1D R C1 1D R C1 1D R C1 1D R C1 1D R C1 3 4 7 8 13 14 17 18 2 5 6 9 12 15 16 19 11 1 |
同様の部品番号 - SN74LV273APWRE4 |
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同様の説明 - SN74LV273APWRE4 |
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