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SN74LV374ADWRE4 データシート(PDF) 2 Page - Texas Instruments |
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SN74LV374ADWRE4 データシート(HTML) 2 Page - Texas Instruments |
2 / 18 page SN54LV374A, SN74LV374A OCTAL EDGETRIGGERED DTYPE FLIPFLOPS WITH 3STATE OUTPUTS SCLS408H − APRIL 1998 − REVISED APRIL 2005 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description/ordering information (continued) These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. terminal assignments 1234 A 1Q OE VCC 8Q B 2D 7D 1D 8D C 3Q 2Q 6Q 7Q D 4D 5D 3D 6D E GND 4Q CLK 5Q FUNCTION TABLE (each flip-flop) INPUTS OUTPUT OE CLK D OUTPUT Q L ↑ H H L ↑ LL L LX Q0 H X X Z GQN PACKAGE (TOP VIEW) 1 234 A B C D E |
同様の部品番号 - SN74LV374ADWRE4 |
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同様の説明 - SN74LV374ADWRE4 |
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