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SN74ABT3614-30PCB データシート(PDF) 5 Page - Texas Instruments |
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SN74ABT3614-30PCB データシート(HTML) 5 Page - Texas Instruments |
5 / 41 page SN74ABT3614 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SCBS126H – JUNE 1992 – REVISED APRIL 2000 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL NAME I/O DESCRIPTION A0 – A35 I/O Port-A data. The 36-bit bidirectional data port for side A. AEA O (port A) Port-A almost-empty flag. Programmable flag synchronized to CLKA. AEA is low when the number of 36-bit words in FIFO2 is less than or equal to the value in offset register X. AEB O (port B) Port-B almost-empty flag. Programmable flag synchronized to CLKB. AEB is low when the number of 36-bit words in FIFO1 is less than or equal to the value in offset register X. AFA O (port A) Port-A almost-full flag. Programmable flag synchronized to CLKA. AFA is low when the number of 36-bit empty locations in FIFO1 is less than or equal to the value in offset register X. AFB O (port B) Port-B almost-full flag. Programmable flag synchronized to CLKB. AFB is low when the number of 36-bit empty locations in FIFO2 is less than or equal to the value in offset register X. B0 – B35 I/O Port-B data. The 36-bit bidirectional data port for side B. BE I Big-endian select. Selects the bytes on port B used during byte or word data transfer. A low on BE selects the most-significant bytes on B0 – B35 for use, and a high selects the least-significant bytes. CLKA I Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or coincident to CLKB. EFA, FFA, AFA, and AEA are synchronized to the low-to-high transition of CLKA. CLKB I Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous or coincident to CLKA. Port-B byte swapping and data-port-sizing operations are also synchronous to the low-to-high transition of CLKB. EFB, FFB, AFB, and AEB are synchronized to the low-to-high transition of CLKB. CSA I Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to read or write data on port A. The A0 – A35 outputs are in the high-impedance state when CSA is high. CSB I Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to read or write data on port B. The B0 – B35 outputs are in the high-impedance state when CSB is high. EFA O (port A) Port-A empty flag. EFA is synchronized to the low-to-high transition of CLKA. When EFA is low, FIFO2 is empty and reads from its memory are disabled. Data can be read from FIFO2 to the output register when EFA is high. EFA is forced low when the device is reset and is set high by the second low-to-high transition of CLKA after data is loaded into empty FIFO2 memory. EFB O (port B) Port-B empty flag. EFB is synchronized to the low-to-high transition of CLKB. When EFB is low, FIFO1 is empty and reads from its memory are disabled. Data can be read from FIFO1 to the output register when EFB is high. EFB is forced low when the device is reset and is set high by the second low-to-high transition of CLKB after data is loaded into empty FIFO1 memory. ENA I Port-A enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A. ENB I Port-B enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B. FFA O (port A) Port-A full flag. FFA is synchronized to the low-to-high transition of CLKA. When FFA is low, FIFO1 is full and writes to its memory are disabled. FFA is forced low when the device is reset and is set high by the second low-to-high transition of CLKA after reset. FFB O (port B) Port-B full flag. FFB is synchronized to the low-to-high transition of CLKB. When FFB is low, FIFO2 is full and writes to its memory are disabled. FFB is forced low when the device is reset and is set high by the second low-to-high transition of CLKB after reset. FS1, FS0 I Flag offset selects. The low-to-high transition of RST latches the values of FS0 and FS1, which selects one of four preset values for the AE flag and AF flag offset. MBA I Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation. When the A0 – A35 outputs are active, a high level on MBA selects data from the mail2 register for output and a low level selects FIFO2 output register data for output. MBF1 O Mail1 register flag. MBF1 is set low by the low-to-high transition of CLKA that writes data to the mail1 register. Writes to the mail1 register are inhibited while MBF1 is low. MBF1 is set high by a low-to-high transition of CLKB when a port-B read is selected and both SIZ1 and SIZ0 are high. MBF1 is set high when the device is reset. MBF2 O Mail2 register flag. MBF2 is set low by the low-to-high transition of CLKB that writes data to the mail2 register. Writes to the mail2 register are inhibited while MBF2 is low. MBF2 is set high by a low-to-high transition of CLKA when a port-A read is selected and MBA is high. MBF2 is set high when the device is reset. |
同様の部品番号 - SN74ABT3614-30PCB |
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同様の説明 - SN74ABT3614-30PCB |
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