SN74ACT3641

1024

× 36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS338C – JANUARY 1994 – REVISED OCTOBER 1997

9

POST OFFICE BOX 655303

output-ready flag (OR)

The OR flag of a FIFO is synchronized to the port clock that reads data from its array (CLKB). When the OR

flag is high, new data is present in the FIFO output register. When the OR flag is low, the previous data word

is present in the FIFO output register and attempted FIFO reads are ignored.

A FIFO read pointer is incremented each time a new word is clocked to its output register. From the time a word

is written to a FIFO, it can be shifted to the FIFO output register in a minimum of three cycles of CLKB; therefore,

an OR flag is low if a word in memory is the next data to be sent to the FIFO output register and three CLKB

cycles have not elapsed since the time the word was written. The OR flag of the FIFO remains low until the third

low-to-high transition of CLKB occurs, simultaneously forcing the OR flag high and shifting the word to the FIFO

output register.

A low-to-high transition on CLKB begins the first synchronization cycle of a write if the clock transition

synchronization cycle (see Figure 6).

input-ready flag (IR)

The IR flag of a FIFO is synchronized to the port clock that writes data to its array (CLKA). When the IR flag is

high, a memory location is free in the SRAM to write new data. No memory locations are free when the IR flag

is low and attempted writes to the FIFO are ignored.

Each time a word is written to a FIFO, its write pointer is incremented. From the time a word is read from a FIFO,

its previous memory location is ready to be written in a minimum of three cycles of CLKA; therefore, an IR flag

is low if less than two cycles of CLKA have elapsed since the next memory write location has been read. The

second low-to-high transition on CLKA after the read sets the IR flag high, and data can be written in the following

cycle.

A low-to-high transition on CLKA begins the first synchronization cycle of a read if the clock transition

synchronization cycle (see Figure 7).

almost-empty flag (AE)

The AE flag of a FIFO is synchronized to the port clock that reads data from its array (CLKB). The almost-empty

state is defined by the contents of register X. This register is loaded with a preset value during a FIFO reset,

programmed from port A, or programmed serially (see

almost-empty flag and almost-full flag offset

programming). The AE flag is low when the FIFO contains X or fewer words and is high when the FIFO contains

(X + 1) or more words. A data word present in the FIFO output register has been read from memory.

Two low-to-high transitions of CLKB are required after a FIFO write for the AE flag to reflect the new level of

fill; therefore, the AE flag of a FIFO containing (X + 1) or more words remains low if two cycles of CLKB have

not elapsed since the write that filled the memory to the (X + 1) level. An AE flag is set high by the second

low-to-high transition of CLKB after the FIFO write that fills memory to the (X + 1) level.

the write that fills the FIFO to (X + 1) words. Otherwise, the subsequent CLKB cycle can be the first

synchronization cycle (see Figure 8).