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SN74ALVC10PW データシート(PDF) 1 Page - Texas Instruments |
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SN74ALVC10PW データシート(HTML) 1 Page - Texas Instruments |
1 / 7 page SN74ALVC10 TRIPLE 3-INPUT POSITIVE-NAND GATE SCES106D – JULY 1997 – REVISED OCTOBER 1998 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process D ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) D Latch-Up Performance Exceeds 250 mA Per JESD 17 D Package Options Include Plastic Small-Outline (D), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages description This triple 3-input positive-NAND gate is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVC10 performs the Boolean function Y = A • B • C or Y = A + B + C in positive logic. The SN74ALVC10 is characterized for operation from –40 °C to 85°C. FUNCTION TABLE (each gate) INPUTS OUTPUT A B C Y H H H L L XX H X LX H X X L H logic symbol† & 1 1A 2 1B 13 1C 1Y 12 3 2A 4 2B 5 2C 2Y 6 9 3A 10 3B 11 3C 3Y 8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Copyright © 1998, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. D, DGV, OR PW PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1A 1B 2A 2B 2C 2Y GND VCC 1C 1Y 3C 3B 3A 3Y PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
同様の部品番号 - SN74ALVC10PW |
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同様の説明 - SN74ALVC10PW |
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