SN74ALVCH16282

18-BIT TO 36-BIT REGISTERED BUS EXCHANGER

WITH 3-STATE OUTPUTS

SCES036D – JULY 1995 – REVISED MARCH 2000

6

POST OFFICE BOX 655303

timing requirements over recommended operating free-air temperature range (unless otherwise

noted) (see Figures 1 through 3)

VCC = 1.8 V

VCC = 2.5 V

± 0.2 V

VCC = 2.7 V

VCC = 3.3 V

± 0.3 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

fclock

Clock frequency

†

150

150

150

MHz

tw

Pulse duration, CLK high or low

†

3.3

3.3

3.3

ns

A data before CLK

↑

†

2.4

2.3

2

t

Setup time

B data before CLK

↑

†

2.2

2.2

1.8

ns

tsu

Setup time

DIR before CLK

↑

†

2.2

2.1

1.7

ns

SEL before CLK

↑

†

2

2

1.8

A data after CLK

↑

†

0.5

0.5

0.7

th

Hold time

B data after CLK

↑

†

0.5

0.5

0.6

ns

th

Hold time

DIR after CLK

↑

†

0.5

0.5

0.5

ns

SEL after CLK

↑

†

0.7

0.7

0.8

† This information was not available at the time of publication.

switching characteristics over recommended operating free-air temperature range (unless

otherwise noted) (see Figures 1 through 3)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 1.8 V

VCC = 2.5 V

± 0.2 V

VCC = 2.7 V

VCC = 3.3 V

± 0.3 V

UNIT

(INPUT)

(OUTPUT)

MIN

TYP

MIN

MAX

MIN

MAX

MIN

MAX

fmax

†

150

150

150

MHz

t d

CLK

A

†

1

6.1

5.5

1.4

5

ns

tpd

CLK

B

†

1.2

6.3

5.7

1.6

5.3

ns

t

OE

A

†

1.3

6.9

6.3

1.2

5.7

ns

ten

OE

B

†

2.3

8.7

8.1

2.3

7.4

ns

tdi

OE

A

†

1.5

7

5.6

1.8

5.7

ns

tdis

OE

B

†

2.1

7.9

6.4

2.3

6.4

ns

† This information was not available at the time of publication.

PARAMETER

TEST CONDITIONS

VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V

UNIT

PARAMETER

TEST CONDITIONS

TYP

TYP

TYP

UNIT

C d

Power dissipation capacitance

Outputs enabled

CL =0

f=10MHz

†

282

310

pF

Cpd

Power dissipation capacitance

Outputs disabled

CL = 0,

f = 10 MHz

†

208

228

pF

† This information was not available at the time of publication.