TLC32040M

ANALOG INTERFACE CIRCUIT

POST OFFICE BOX 655303

4–6

explanation of internal timing configuration

All of the internal timing of the AIC is derived from the high-frequency clock signal that drives the master clock

input. The shift clock signal, which strobes the serial port data between the AIC and DSP, is derived by dividing

the master clock input signal frequency by four.

SCF Clock Frequency

+

Master Clock Frequency

2

Contents of Counter A

Conversion Frequency

+

SCF Clock Frequency

Contents of Counter B

Shift Clock Frequency

+

Master Clock Frequency

4

TX Counter A and TX Counter B, which are driven by the master clock signal, determine the D/A conversion

timing. Similarly, RX Counter A and RX Counter B determine the A/D conversion timing. In order for the

switched-capacitor low-pass and band-pass filters to meet their transfer function specifications, the frequency

of the clock inputs of the switched-capacitor filters must be 288 kHz. If the frequencies of the clock inputs are

not 288 kHz , the filter transfer function frequencies are scaled by the ratios of the clock frequencies to 288 kHz.

Thus, to obtain the specified filter responses, the combination of master clock frequency and TX Counter A and

RX Counter A values must yield 288-kHz switched-capacitor clock signals. These 288-kHz clock signals can

then be divided by TX Counter B and RX Counter B to establish the D/A and A/D conversion timings.

TX Counter A and TX Counter B are reloaded every D/A conversion period, while RX Counter A and RX Counter

B are reloaded every A/D conversion period. TX Counter B and RX Counter B are loaded with the values in the

TB and RB Registers, respectively. Via software control, TX Counter A can be loaded with either TA Register,

the TA Register less the TA’ Register, or the TA Register plus the TA’ Register. By selecting the TA Register less

the TA’ Register option, the upcoming conversion timing will occur earlier by an amount of time that equals TA’

times the signal period of the master clock. By selecting the TA Register plus the TA’ Register option, the

upcoming conversion timing will occur later by an amount of time that equals TA’ times the signal period of the

master clock. Thus the D/A conversion timing can be advanced or retarded. An identical ability to alter the A/D

conversion timing is provided. In this case, however, the RX Counter A can be programmed via software control

with the RA Register, the RA Register less the RA’ Register, or the RA Register plus the RA’ Register.

The ability to advance or retard conversion timing is particularly useful for modem applications. This feature

allows controlled changes in the A/D and D/A conversion timing. This feature can be used to enhance signal-to-

noise performance, to perform frequency-tracking functions, and to generate nonstandard modem frequencies.

If the transmit and receive sections are configured to be synchronous (see the WORD/BYTE description in the

Terminal Functions table), then both the low-pass and band-pass switched-capacitor filter clocks are derived

from TX Counter A. Also, both the D/A and A/D conversion timing are derived from TX Counter A and TX Counter

B. When the transmit and receive sections are configured to be synchronous, the RX Counter A, RX Counter

B, RA Register, RA’ Register, and RB Registers are not used.