TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I

VOICE-BAND ANALOG INTERFACE CIRCUITS

SLAS017F – MARCH 1988 – REVISED MAY 1995

3

POST OFFICE BOX 655303

functional block diagram

M

U

X

M

U

X

IN +

IN –

AUX IN +

AUX IN –

Internal

Voltage

Reference

SHIFT CLK

MSTER CLK

EODR

DR

FSR

WORD/BYTE

DX

FSX

EODX

SERIAL

PORT

A/D

OUT +

OUT –

M

U

X

D/A

sin x/x

Correction

Filter

Filter

Transmit Section

VCC + VCC – ANLG

GND

DTGL

GND

VDD

(Digital)

REF

RESET

Receive Section

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

ANLG GND

17,18

Analog ground return for all internal analog circuits. Not internally connected to DGTL GND.

AUX IN +

24

I

Noninverting auxiliary analog input stage. AUX IN + can be switched into the bandpass filter and A/D

t

th i

ft

t l If th

i t bit i th

t l

i t

i

1 th

ili

i

t

converter path via software control. If the appropriate bit in the control register is a 1, the auxiliary inputs

will replace the IN + and IN – inputs. If the bit is a 0, the IN + and IN – inputs will be used (see the AIC DX

will re lace the IN + and IN – in uts. If the bit is a 0, the IN + and IN – in uts will be used (see the AIC DX

data word format section).

AUX IN –

23

I

Inverting auxiliary analog input (see the above AUX IN + description).

DGTL GND

9

Digital ground for all internal logic circuits. Not internally connected to ANLG GND.

DR

5

O

Data receive. DR is used to transmit the ADC output bits from the AIC to the TMS320 (SMJ320) serial port.

This transmission of bits from the AIC to the TMS320 (SMJ320) serial port is synchronized with the SHIFT

CLK signal.

DX

12

I

Data transmit. DX is used to receive the DAC input bits and timing and control information from the TMS320

(SMJ320). This serial transmission from the TMS320 (SMJ320) serial port to the AIC is synchronized with

the SHIFT CLK signal.

EODR

3

O

End of data receive. (See the WORD/BYTE description and Serial Port Timing diagram.) During the

word-mode timing, EODR is a low-going pulse that occurs immediately after the 16 bits of A/D information

have been transmitted from the AIC to the TMS320 (SMJ320) serial port. EODR can be used to interrupt

a microprocessor upon completion of serial communications. Also, EODR can be used to strobe and enable

external serial-to-parallel shift registers, latches, or external FIFO RAM, and to facilitate parallel data bus

communications between the AIC and the serial-to-parallel shift registers. During the byte-mode timing,

EODR goes low after the first byte has been transmitted from the AIC to the TMS320 (SMJ320) serial port

and is kept low until the second byte has been transmitted. The DSP can use this low-going signal to

differentiate between the two bytes as to which is first and which is second. EODR does not occur after

secondary communication.