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ISL12058IUZ データシート(PDF) 11 Page - Intersil Corporation

部品番号 ISL12058IUZ
部品情報  Low Cost and Low Power I2C-Bus??Real Time Clock/Calendar
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メーカー  INTERSIL [Intersil Corporation]
ホームページ  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL12058IUZ データシート(HTML) 11 Page - Intersil Corporation

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11
FN6756.0
June 15, 2009
FREQUENCY OUT CONTROL BITS (FO <1:0>)
These bits select the output frequency at the IRQ/FOUT pin.
IRQE must be set to “0” for frequency output at the
IRQ/FOUT pin. Refer to Table 5 for frequency selection.
ALARM ENABLE BITS (ALM1E, ALM2E)
This bit enables/disables the Alarm1 and Alarm2 function.
When the ALM1E bit is set to “1”, the Alarm1 function is
enabled. When the ALM1E is cleared to “0”, the alarm function
is disabled. ALM1E bit is set to “0” at power-up.
When the ALM2E bit is set to “1”, the Alarm2 function is
enabled. When the ALM2E is cleared to “0”, the alarm function
is disabled. ALM2E bit is set to “0” at power-up.
NOTE: The Alarm1 has hardware function via the IRQ/FOUT pin.
Alarm2 does not have hardware interrupt function.
Alarm1 Registers
Addresses [Address 0Ch to 11h]
The Alarm1 register bytes are set up identical to the RTC
register bytes, except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
alarm registers (seconds, minutes, etc) are used to make the
comparison. Note that there is no alarm byte for year. When
all the enable bits are set to “0” with ALM1E set to “1”, the
Alarm 1 will triggered once a second.
The Alarm1 function works as a comparison between the
Alarm1 registers and the RTC registers. As the RTC
advances, the Alarm1 will be triggered once a match occurs
between the Alarm1 registers and the RTC registers. Any
one Alarm1 register, multiple registers, or all registers can be
enabled for a match.
To clear an Alarm1, the A1F status bit can be set to “0” with a
write or use the ARST bit auto reset function.
Following is example of Alarm1 Interrupt.
Example – A single alarm will occur on January 1 at
11:30am.
A. Set Alarm1 registers as follows:
10
FOUT
1
1
Alarm 1 Interrupt
TABLE 5. FREQUENCY SELECTION OF IRQ/FOUT PIN WITH
FO1 AND FO0 BITS
FO1
FO0
FREQUENCY,
FOUT (Hz)
COMMENT
1
1
32768
Free running crystal clock
1
0
8192
Free running crystal clock
0
1
4096
Free running crystal clock
0
0
1
Sync. at RTC write
TABLE 4. FUNCTION SELECTION OF IRQ/FOUT PIN WITH
A1E AND IRQE BITS (Continued)
A1E
IRQE
IRQ/FOUT FUNCTION
TABLE 6. ALARM1 INTERRUPT WITH ENABLE BITS SELECTION
A1M1
A1M2
A1M3
A1M4
A1M5
A1M6
ALARM1
Interrupt
00
000
0
Every Second
10
000
0
Match Second
01
000
0
Match Minute
00
100
0
Match Hour
00
010
0
Match Date
00
001
0
Match Month
00
000
1
Match Day
1
1
0
0
0
0
Match Second
and Minute
1
0
1
0
0
0
Match Second
and Hour
1
1
1
0
0
0
Match Second,
Minute, and Hour
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
00
011
1
Match Date,
Month, and Day
1
0
0
1
1
1
Match Second,
Date, Month, and
Day
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
01
111
1
Match MInute,
Hour, Date,
Month, and Day
1
1
1
1
1
1
Match Second,
MInute, Hour,
Date, Month, and
Day
ISL12058


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