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CS5364-CQZ データシート(PDF) 9 Page - Cirrus Logic |
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CS5364-CQZ データシート(HTML) 9 Page - Cirrus Logic |
9 / 42 page DS625F4 9 CS5364 2. TYPICAL CONNECTION DIAGRAM Figure 2. Typical Connection Diagram For analog buffer configurations, refer to Cirrus Application Note AN241. Also, a low-cost single-ended-to-differen- tial solution is provided on the Customer Evaluation Board. FILT+ D + VA V +5V 5.1 Ω 1 μF + SDOUT2 DIF0/AD0/CS Power Down and Mode Settings 0.01 μF MODE0/SDA/CDOUT MODE1/SCL/CCLK REF_GND VLC AIN + 1 AIN - 1 Channel 1 Analog Input Buffer AIN + 2 AIN - 2 Channel 2 Analog Input Buffer AIN + 3 AIN - 3 Channel 3 Analog Input Buffer AIN + 4 AIN - 4 Channel 4 Analog Input Buffer 0.1 μF VQ GND 220 μF 0.1 μF + 1 μF GND DIF1/AD1/CDIN RST OVFL 0.01 0.01 μF +5V to 3.3V 1 μF + A/D CONVERTER CS5364 SDOUT1/TDM SCLK MCLK Timing Logic and Clock Audio Data Processor MDIV CLKMODE 6 40 36 37 38 41 42 34 30 27 31 24 25 23 LRCK/FS 26 RESERVED +5V to 1.8V 5 7 8 47 48 1 2 13 14 11 12 3, 8,10, 15, 16, 17, 18, 19, 29, 32, 43, 44, 45, 46 33 4, 9 35 VLS +5V to 1.8V 28 XTI XTO 21 22 +5V VX 20 Resistor may only be used if VD is derived from VA. If used, do not drive any other logic from VD. 0.01 μF μF TDM |
同様の部品番号 - CS5364-CQZ |
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同様の説明 - CS5364-CQZ |
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