データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

AD7781 データシート(PDF) 11 Page - Analog Devices

部品番号 AD7781
部品情報  20-Bit, Pin-Programmable, Low Power Sigma-Delta ADC
Download  16 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD7781 データシート(HTML) 11 Page - Analog Devices

Back Button AD7781 Datasheet HTML 7Page - Analog Devices AD7781 Datasheet HTML 8Page - Analog Devices AD7781 Datasheet HTML 9Page - Analog Devices AD7781 Datasheet HTML 10Page - Analog Devices AD7781 Datasheet HTML 11Page - Analog Devices AD7781 Datasheet HTML 12Page - Analog Devices AD7781 Datasheet HTML 13Page - Analog Devices AD7781 Datasheet HTML 14Page - Analog Devices AD7781 Datasheet HTML 15Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 11 / 16 page
background image
AD7781
Rev. 0 | Page 11 of 16
THEORY OF OPERATION
0120
100
80
60
40
20
INPUT SIGNAL FREQUENCY (Hz)
–120
0
–20
–40
–60
–80
–100
The AD7781 is a low power ADC that incorporates a precision,
20-bit, Σ-Δ modulator; a PGA; and an on-chip digital filter
intended for measuring wide dynamic range, low frequency
signals. The part provides a complete front-end solution for
bridge sensor applications such as weigh scales and pressure
sensors.
The device has an internal clock and one buffered differential
input. It offers a choice of two update rates (10 Hz or 16.7 Hz)
and two gain settings (1 or 128). These functions are controlled
using dedicated pins, which makes the interface easy to configure.
A 2-wire interface simplifies data retrieval from the AD7781.
FILTER, DATA RATE, AND SETTLING TIME
The AD7781 has two filter options. When the FILTER pin is
low, the 16.7 Hz filter is selected; when the FILTER pin is high,
the 10 Hz filter is selected. When the polarity of the FILTER pin
is changed, the AD7781 modulator and filter are reset immedi-
ately. DOUT/RDY is set high, and the ADC begins conversions
using the selected filter response. The first conversion requires
the total settling time of the filter. Subsequent conversions
occur at the selected update rate. The settling time of the 10 Hz
filter is 300 ms (three conversion cycles), and the settling time
of the 16.7 Hz filter is 120 ms (two conversion cycles).
When a step change occurs on the analog input, the AD7781
requires several conversion cycles to generate a valid conversion.
If the step change occurs synchronous to the conversion period, the
settling time of the AD7781 must be allowed to generate a valid
conversion. If the step change occurs asynchronous to the end
of a conversion, an extra conversion must be allowed to generate
a valid conversion. The data register is updated with all the con-
versions, but, for an accurate result, the user must allow for the
required time.
Figure 20 and Figure 21 show the filter response for each filter.
The 10 Hz filter provides more than −45 dB of rejection in the
stop band. The only external filtering required on the analog
inputs is a simple R-C filter to provide rejection at multiples of
the master clock. A 1 kΩ resistor in series with each analog input,
a 0.01 μF capacitor from each input to GND, and a 0.1 μF
capacitor from AIN(+) to AIN(−) are recommended.
When the filter is changed, DOUT/RDY goes high and remains
high until the appropriate settling time for that filter elapses
(see
). Therefore, the user should complete any read
operations before changing the filter. Otherwise, 1s are read
back from the AD7781 because the DOUT/
Figure 5
RDY pin is set high
following the filter change.
Figure 20. Filter Profile with Update Rate = 16.7 Hz (FILTER = 0)
0
120
100
80
60
40
20
INPUT SIGNAL FREQUENCY (Hz)
–120
0
–20
–40
–60
–80
–100
Figure 21. Filter Profile with Update Rate = 10 Hz (FILTER = 1)
GAIN
The AD7781 has two gain options: gain = 1 and gain = 128.
When the GAIN pin is low, the gain is set to 128; when the
GAIN pin is high, the gain is set to 1. The acceptable analog
input range is ±VREF/gain. Thus, with VREF = 5 V, the input range
is ±5 V when GAIN is high and ±39 mV when GAIN is low.
When the polarity of the GAIN pin is changed, the AD7781 modu-
lator and filter are reset immediately. DOUT/RDY is set high, and
the ADC begins conversions. DOUT/RDY remains high until
the appropriate settling time for the filter elapses (see
).
Therefore, the user should complete any read operations before
changing the gain. Otherwise, 1s are read back from the AD7781
because the DOUT/
Figure 5
RDY pin is set high following the gain change.
The total settling time of the selected filter is required to generate
the first conversion after the gain change; subsequent conversions
occur at the selected update rate.


同様の部品番号 - AD7781

メーカー部品番号データシート部品情報
logo
Analog Devices
AD7781 AD-AD7781 Datasheet
326Kb / 17P
   20-Bit, Pin-Programmable Low Power Sigma-Delta ADC
AD7781BRUZ AD-AD7781BRUZ Datasheet
326Kb / 17P
   20-Bit, Pin-Programmable Low Power Sigma-Delta ADC
AD7781BRUZ-REEL AD-AD7781BRUZ-REEL Datasheet
326Kb / 17P
   20-Bit, Pin-Programmable Low Power Sigma-Delta ADC
AD7781BRZ AD-AD7781BRZ Datasheet
326Kb / 17P
   20-Bit, Pin-Programmable Low Power Sigma-Delta ADC
AD7781BRZ-REEL AD-AD7781BRZ-REEL Datasheet
326Kb / 17P
   20-Bit, Pin-Programmable Low Power Sigma-Delta ADC
More results

同様の説明 - AD7781

メーカー部品番号データシート部品情報
logo
Analog Devices
AD7781 AD-AD7781_17 Datasheet
326Kb / 17P
   20-Bit, Pin-Programmable Low Power Sigma-Delta ADC
AD7780 AD-AD7780 Datasheet
429Kb / 16P
   24-Bit, Pin-Programmable, Ultralow Power Sigma-Delta ADC
REV. A
AD7780 AD-AD7780_17 Datasheet
356Kb / 17P
   24-Bit, Pin-Programmable, Ultralow Power Sigma-Delta ADC
logo
Core Technology (Shenzh...
CS1180 CHIPSEA-CS1180 Datasheet
757Kb / 30P
   20-bit Sigma-Delta ADC
logo
Cirrus Logic
CS5510 CIRRUS-CS5510 Datasheet
406Kb / 24P
   16-bit and 20-bit, 8-pin Sigma-Delta ADC
logo
Analog Devices
AD7170 AD-AD7170 Datasheet
271Kb / 16P
   12-Bit Low Power Sigma-Delta ADC
REV. 0
AD7171 AD-AD7171 Datasheet
284Kb / 16P
   16-Bit Low Power Sigma-Delta ADC
REV. 0
AD7171 AD-AD7171_17 Datasheet
313Kb / 17P
   16-Bit, Low Power, Sigma-Delta ADC
AD7170 AD-AD7170_17 Datasheet
370Kb / 15P
   12-Bit Low Power Sigma-Delta ADC
AD7791 AD-AD7791_17 Datasheet
525Kb / 21P
   Low Power, Buffered 24-Bit Sigma-Delta ADC
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16


データシート ダウンロード

Go To PDF Page


リンク URL




プライバシーポリシー
ALLDATASHEET.JP
ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com