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ADuM4160BRWZ データシート(PDF) 8 Page - Analog Devices

部品番号 ADuM4160BRWZ
部品情報  Full/Low Speed USB Digital Isolator
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
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ADuM4160BRWZ データシート(HTML) 8 Page - Analog Devices

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ADuM4160
Rev. A | Page 8 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VBUS1 1
GND1* 2
VDD1 3
PDEN
4
VBUS2
16
GND2*
15
VDD2
14
SPD
13
SPU
5
PIN
12
UD–
6
DD–
11
UD+
7
DD+
10
GND1* 8
GND2*
9
ADuM4160
TOP VIEW
(Not to Scale)
NC = NO CONNECT
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND CONNECTING
BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY
CONNECTED, AND CONNECTING BOTH TO GND2 IS RECOMMENDED.
Figure 3. Pin Configuration
Table 9. Pin Function Descriptions
Pin No.
Mnemonic Direction Description
1
VBUS1
Power
Input Power Supply for Side 1. Where the isolator is powered by the USB bus voltage, 4.5 V to 5.5 V,
connect VBUS1 to the USB power bus. Where the isolator is powered from a 3.3 V power supply, connect
VBUS1 to VDD1 and to the external 3.3 V power supply. Bypass to GND1 is required.
2
GND1
Return
Ground 1. Ground reference for Isolator Side 1.
3
VDD1
Power
Power Supply for Side 1. Where the isolator is powered by the USB bus voltage, 4.5 V to 5.5 V, the VDDI pin
should be used for a bypass capacitor to GND1. Signal lines that may require pull up, such as PDEN and
SPU, should be tied to this pin. Where the isolator is powered from a 3.3 V power supply, connect VBUS1 to
VDD1 and to the external 3.3 V power supply. Bypass to GND1 is required.
4
PDEN
Input
Pull-Down Enable. This pin is read when exiting reset. For standard operation, connect this pin to VDD1.
When connected to GND1 while exiting from reset, the downstream pull-down resistors are
disconnected, allowing buffer impedance measurements.
5
SPU
Input
Speed Select Upstream Buffer. Active high logic input. Selects full speed slew rate, timing, and logic
conventions when SPU is high, and low speed slew rate, timing, and logic conventions when SPU is tied
low. This input must be set high via connection to VDD1 or set low via connection to GND1 and must
match Pin 13.
6
UD−
I/O
Upstream D−.
7
UD+
I/O
Upstream D+.
8
GND1
Return
Ground 1. Ground reference for Isolator Side 1.
9
GND2
Return
Ground 2. Ground reference for Isolator Side 2.
10
DD+
I/O
Downstream D+.
11
DD−
I/O
Downstream D−.
12
PIN
Input
Upstream Pull-Up Enable. PIN controls the power connection to the pull-up for the upstream port. It can
be tied to VDD2 for operation on power-up, or tied to an external control signal for applications requiring
delayed enumeration.
13
SPD
Input
Speed Select Downstream Buffer. Active high logic input. Selects full speed slew rate, timing, and logic
conventions when SPD is high, and low speed slew rate, timing, and logic conventions when SPD is tied
low. This input must be set high via connection to VDD2 or low via connection to GND2, and must match
Pin 5.
14
VDD2
Power
Power Supply for Side 2. Where the isolator is powered by the USB bus voltage, 4.5 V to 5.5 V, the VDD2
pin should be used for a bypass capacitor to GND2. Signal lines that may require pull-up, such as SPD,
can be tied to this pin. Where the isolator is powered from a 3.3 V power supply, connect VBUS2 to VDD2
and to the external 3.3 V power supply. Bypass to GND2 is required.
15
GND2
Return
Ground 2. Ground reference for Isolator Side 2.
16
VBUS2
Power
Input Power Supply for Side 2. Where the isolator is powered by the USB bus voltage, 4.5 V to 5.5 V,
connect VBUS2 to the USB power bus. Where the isolator is powered from a 3.3 V power supply, connect
VBUS2 to VDD2 and to the external 3.3 V power supply. Bypass to GND2 is required.


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