SA1021

HANGZHOU SILAN MICROELECTRONICS CO.,LTD

REV:2.0

2004.07.31

Http: www.silan.com.cn

Page 5 of 7

TEST AND APPLICATION CIRCUIT

Fig.8: Stereo application in combination with a low voltage PLL stereo decoder (UTC7040) and a low voltage

Mono/stereo power amplifier (UTC7050).

Fig.9 test set-up; Vi=30mV; fi=76kHz; selective voltmeter at output has Ri

≥1MΩ and Ci≤8pF; fo=fi.

This test set-up is to incorporate the circuit of Fig.5 for mono operation or the circuit of Fig.8 for stereo operation.

For either circuit, replace the 100

µF capacitor at pin 6 with R6(100kΩ) as shown above.

SELECTIVITY

S+300=20

fi

|

Vo

fi)

-

(300KhZ

|

Vo

S-300=20

fi

|

Vo

fi)

(300KhZ

|

Vo

+